Abstract: A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.

Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

Abstract: Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

Abstract: In a high voltage switch circuit for programming memory cells, preset devices for precharging the core circuit are eliminated by statically presetting nodes of the switch core circuit through a pair of drive circuits arranged to pull up or down a pair of cascoded transistors in the core circuit.

Abstract: Circuits are provided for high-voltage switching in single-well CMOS processes.

Abstract: Non-Volatile Memory (NVM) cells include a selection circuit for providing an output based on selecting between an input data signal and an output of a Multiple Time Programmable (MTP) NVM element. The input data signal may be latched by a latch circuit such as a flip-flop first. The selector circuit's output is used to confirm the programming values for the MTP NVM element such that the element can be programmed correctly without losing time by reading the programmed MTP NVM element or reprogramming a misprogrammed element.

Abstract: An RFID tag has a Non Volatile Memory (NVM) array that can store data in a way that survives loss of power. The data is configuration data that controls the operation of an operational component of the tag. A performance of the operational component is thus adjusted according to the configuration data, and the adjustment is retained.

Abstract: An RFID tag has a fuse that is adapted to store configuration data in a way that survives loss of power. The fuse can be one time programmable or many times programmable, and be implemented with a non-volatile memory. The configuration data becomes available to an operational component of the tag, such as at power up, controlling its performance.

Abstract: An RFID tag includes a non-volatile memory (NVM) circuit with at least two distinct types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.

Abstract: A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.

Abstract: Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

Abstract: Memory devices have cells for storing data, and transmit a completion signal when a task is completed. Interfaces, software and methods use the completion signal to control such memory devices. In one embodiment, an interface asserts a continuous task signal on the memory, and deasserts it when it senses the completion signal. In one embodiment, a memory discontinues the completion signal when the task signal is deasserted. RFID tags according to the invention include a memory device that transmits a completion signal to an interface. The interface may be external to the RFID tag, or also hosted on it.

Abstract: Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

Abstract: Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors. An amount of charge stored on the floating gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

Abstract: A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.

Abstract: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage which can be used to represent information such as binary bits. A control capacitor structure having its first terminal coupled to a first voltage source and its second terminal coupled to the floating gate and a tunneling capacitor structure having its first terminal coupled to a second voltage source and its second terminal coupled to the floating gate are utilized in each embodiment. The control capacitor structure is fabricated so that it has much more capacitance than does the tunneling capacitor structure (and assorted stray capacitance between the floating gate and various other nodes of the cell).

Abstract: Circuits are provided for high-voltage switching in single-well CMOS processes.

Abstract: Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.

Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

Abstract: Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.