Patents by Inventor Alessandro Calderoni

Alessandro Calderoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230298652
    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage stru
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E. Fackenthal, Duane R. Mills
  • Patent number: 11711924
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 11688450
    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage stru
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E Fackenthal, Duane R. Mills
  • Patent number: 11501817
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
  • Publication number: 20220278112
    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage stru
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E. Fackenthal, Duane R. Mills
  • Patent number: 11393978
    Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
  • Publication number: 20220199634
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 11315939
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Publication number: 20210280231
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 9, 2021
    Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
  • Patent number: 11024378
    Abstract: Memory systems and memory programming methods are described.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 1, 2021
    Assignee: Micron Technology , Inc.
    Inventors: Emiliano Faraoni, Scott E. Sills, Alessandro Calderoni, Adam Johnson
  • Publication number: 20210134816
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 22, 2020
    Publication date: May 6, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 10978128
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
  • Patent number: 10903218
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Publication number: 20200365800
    Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 19, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
  • Patent number: 10833092
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Publication number: 20200328221
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 15, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 10741755
    Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
  • Publication number: 20200235111
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 10706906
    Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10707220
    Abstract: Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Alessandro Calderoni, D. V. Nirmal Ramaswamy