Patents by Inventor Alessandro Calderoni
Alessandro Calderoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10707220Abstract: Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.Type: GrantFiled: August 31, 2017Date of Patent: July 7, 2020Assignee: Micron Technology, Inc.Inventors: Ashonita A. Chavan, Alessandro Calderoni, D. V. Nirmal Ramaswamy
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Patent number: 10699784Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: GrantFiled: August 7, 2018Date of Patent: June 30, 2020Assignee: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Publication number: 20200090728Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.Type: ApplicationFiled: September 27, 2019Publication date: March 19, 2020Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
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Patent number: 10475500Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.Type: GrantFiled: August 23, 2018Date of Patent: November 12, 2019Assignee: Micron Technology, Inc.Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
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Patent number: 10431285Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may have a polarity opposite to the access voltage. A delay may be instituted between access attempts in order to discharge the untargeted memory cells.Type: GrantFiled: November 8, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Bei Wang, Alessandro Calderoni, Wayne Kinney, Adam Johnson, Durai Vishak Nirmal Ramaswamy
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Publication number: 20190139591Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.Type: ApplicationFiled: November 8, 2018Publication date: May 9, 2019Inventors: Bei Wang, Alessandro Calderoni, Wayne Kinney, Adam Johnson, Durai Vishak Nirmal Ramaswamy
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Publication number: 20190074060Abstract: Memory systems and memory programming methods are described.Type: ApplicationFiled: October 31, 2018Publication date: March 7, 2019Applicant: Micron Technology, Inc.Inventors: Emiliano Faraoni, Scott E. Sills, Alessandro Calderoni, Adam Johnson
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Publication number: 20180366176Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.Type: ApplicationFiled: August 23, 2018Publication date: December 20, 2018Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
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Publication number: 20180358076Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.Type: ApplicationFiled: July 24, 2018Publication date: December 13, 2018Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy
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Patent number: 10153026Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.Type: GrantFiled: December 29, 2017Date of Patent: December 11, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Bei Wang, Alessandro Calderoni, Wayne Kinney, Adam Johnson, Durai Vishak Nirmal Ramaswamy
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Patent number: 10147486Abstract: Memory systems and memory programming methods are described.Type: GrantFiled: February 22, 2016Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Emiliano Faraoni, Scott E. Sills, Alessandro Calderoni, Adam Johnson
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Publication number: 20180342294Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Patent number: 10141040Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.Type: GrantFiled: August 31, 2017Date of Patent: November 27, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy
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Patent number: 10134982Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.Type: GrantFiled: July 24, 2015Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
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Publication number: 20180331283Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.Type: ApplicationFiled: July 20, 2018Publication date: November 15, 2018Applicant: Micron Technology, Inc.Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
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Patent number: 10083732Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.Type: GrantFiled: July 10, 2017Date of Patent: September 25, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy, Kirk Prall, Ferdinando Bedeschi
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Patent number: 10062432Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: GrantFiled: May 21, 2015Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Publication number: 20180137908Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.Type: ApplicationFiled: December 29, 2017Publication date: May 17, 2018Inventors: Bei Wang, Alessandro Calderoni, Wayne Kinney, Adam Johnson, Durai Vishak Nirmal Ramaswamy
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Patent number: 9928894Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.Type: GrantFiled: February 21, 2017Date of Patent: March 27, 2018Assignee: MICRON TECHNOLOGY, INCInventors: Bei Wang, Alessandro Calderoni, Wayne Kinney, Adam Johnson, Durai Vishak Nirmal Ramaswamy
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Publication number: 20180005681Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.Type: ApplicationFiled: August 31, 2017Publication date: January 4, 2018Inventors: Alessandro Calderoni, Durai Vishak Nirmal Ramaswamy