Patents by Inventor Alessandro Chini

Alessandro Chini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218231
    Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 4, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Publication number: 20250040173
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ferdinando IUCOLANO, Alessandro Chini
  • Patent number: 12148823
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: November 19, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Publication number: 20240332413
    Abstract: The HEMT device has a body including a heterostructure configured to generate a 2-dimensional charge-carrier gas; and a gate structure which extends on a top surface of the body and is biasable to electrically control the 2-dimensional charge-carrier gas. The gate structure has a channel modulating region of semiconductor material; a functional region of semiconductor material; and a gate contact region of conductive material. The functional region and the gate contact region extend on a top surface of the channel modulating region and the gate contact region is arranged laterally with respect to the functional region. The channel modulating region has a different conductivity type with respect to the functional region.
    Type: Application
    Filed: March 21, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Ferdinando IUCOLANO, Alessandro CHINI, Maria Eloisa CASTAGNA, Aurore CONSTANT, Cristina TRINGALI
  • Publication number: 20240313102
    Abstract: An integrated power device includes a heterostructure, having a channel layer and a barrier layer, a source contact, a drain contact, and a gate region, arranged on the barrier layer between the source contact and the drain contact. An insulating field structure is arranged on the barrier layer between the gate region and the drain contact. A field plate extends over the insulating field structure. The insulating field structure includes a first dielectric region made of a first dielectric material on the barrier layer and a second dielectric region made of a second dielectric material, selectively etchable with respect to the first dielectric material on the first dielectric region. On a side of the insulating field structure towards the gate region, the field plate is in contact with the first dielectric region.
    Type: Application
    Filed: March 5, 2024
    Publication date: September 19, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Cristina MICCOLI, Ferdinando IUCOLANO, Cristina TRINGALI, Maria Eloisa CASTAGNA, Alessandro CHINI
  • Publication number: 20240178301
    Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Application
    Filed: December 5, 2023
    Publication date: May 30, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando IUCOLANO, Alfonso PATTI, Alessandro CHINI
  • Patent number: 11862707
    Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alfonso Patti, Alessandro Chini
  • Publication number: 20230282727
    Abstract: An HEMT device includes a heterostructure, an insulation layer that extends on the heterostructure and has a thickness along a first direction, and a gate region. The gate region has a first portion that extends through the insulation layer, throughout the thickness of the insulation layer, and has a second portion that extends in the heterostructure. The first portion of the gate region has a first width along a second direction transverse to the first direction. The second portion of the gate region has a second width, along the second direction, that is different from the first width.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 7, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando IUCOLANO, Alessandro CHINI
  • Publication number: 20230047815
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Application
    Filed: October 31, 2022
    Publication date: February 16, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando IUCOLANO, Alessandro CHINI
  • Patent number: 11489068
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: November 1, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Publication number: 20210367062
    Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando IUCOLANO, Alfonso PATTI, Alessandro CHINI
  • Patent number: 11101363
    Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 24, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alfonso Patti, Alessandro Chini
  • Publication number: 20210175350
    Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 10, 2021
    Inventors: Ferdinando IUCOLANO, Alessandro Chini
  • Publication number: 20210091218
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Inventors: Ferdinando IUCOLANO, Alessandro CHINI
  • Patent number: 10892357
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: January 12, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Publication number: 20200091313
    Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 19, 2020
    Inventors: Ferdinando IUCOLANO, Alfonso PATTI, Alessandro Chini
  • Patent number: 10522646
    Abstract: A HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 31, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alfonso Patti, Alessandro Chini
  • Patent number: 10516041
    Abstract: An HEMT includes a buffer layer, a hole-supply layer on the buffer layer, a heterostructure on the hole-supply layer, and a source electrode. The hole-supply layer is made of P-type doped semiconductor material, the buffer layer is doped with carbon, and the source electrode is in direct electrical contact with the hole-supply layer, such that the hole-supply layer can be biased to facilitate the transport of holes from the hole-supply layer to the buffer layer.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 24, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Publication number: 20190288100
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Inventors: Ferdinando IUCOLANO, Alessandro CHINI
  • Patent number: 10381470
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 13, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alessandro Chini