Abstract: A clock signal synchronizing device includes a first delay unit with variable delay time connected to an input circuit with a first delay time which receives a first clock signal and outputs a second clock signal. A second delay unit has a fixed delay time portion corresponding to the first delay time, and an additional variable delay time portion. A first phase comparison unit has a first input connected to the output of the input circuit, and a second input connected to the output of the second delay unit. The output signal controls the delay time of the first delay unit. A copy of the input circuit has an input connected to the output of the first delay unit. A second phase comparison unit has an input connected to the output of the copy, and an output signal controls the variable delay time portion of the second delay unit.

Abstract: The invention creates a delay control apparatus for provision of clock signals in circuit units having a delay device (100) comprising a first delay element (101) for provision of a variable time delay (105) between an output signal (104) and an input signal (103) for the first delay element (101), a feedback device (106) for feeding back the output signal (104) and a phase difference detection device (108) for detection of a phase difference between the input signal (103) and the fed-back output signal (107). The phase difference detection device emits a control signal (109) for controlling the first delay element (101) as a function of the detected phase difference, while a further, second delay element (102) which is connected in series with the first delay element (101), produces an additional delay as a function of a frequency of the output signal (103) which is detected by a frequency detection unit (110).

Abstract: An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.

Abstract: A phase detector has a reference signal input for a reference signal and a detector input for a signal to be evaluated. A memory unit is connected to the detector input and stores a state of the signal to be evaluated at a storage instant. An evaluation unit is connected downstream of the storage unit and is designed in such a way that it can be used to compare the stored state of the signal with the state of the reference signal at an evaluation instant and to generate an evaluation result signal therefrom. The phase detector has a control unit for prescribing the storage instant and the evaluation instant, the control unit prescribing the storage instant first and then the evaluation instant. A detector output is connected to the evaluation unit and the evaluation result signal can be tapped off at the detector output.

Abstract: An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.