Patents by Inventor Alessandro Torsi
Alessandro Torsi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10515696Abstract: Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.Type: GrantFiled: July 22, 2014Date of Patent: December 24, 2019Assignee: Micron Technology, Inc.Inventor: Alessandro Torsi
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Patent number: 9419220Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.Type: GrantFiled: July 22, 2015Date of Patent: August 16, 2016Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Sanh D. Tang, Alessandro Torsi, Muralikrishnan Balakrishnan, Xiaonan Chen, John K. Zahurak
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Publication number: 20150333257Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.Type: ApplicationFiled: July 22, 2015Publication date: November 19, 2015Inventors: D.V. Nirmal Ramaswamy, Sanh D. Tang, Alessandro Torsi, Muralikrishnan Balakrishnan, Xiaonan Chen, John K. Zahurak
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Patent number: 9112138Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.Type: GrantFiled: June 14, 2012Date of Patent: August 18, 2015Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Sanh D. Tang, Alessandro Torsi, Muralikrishnan Balakrishnan, Xiaonan Chen, John K. Zahurak
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Patent number: 8891309Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.Type: GrantFiled: October 13, 2011Date of Patent: November 18, 2014Assignee: Micron Technology, Inc.Inventors: Seiichi Aritome, Alessandro Torsi, Carlo Musilli
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Publication number: 20140334223Abstract: Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.Type: ApplicationFiled: July 22, 2014Publication date: November 13, 2014Inventor: Alessandro Torsi
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Patent number: 8859329Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: GrantFiled: April 23, 2014Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Publication number: 20140231743Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: ApplicationFiled: April 23, 2014Publication date: August 21, 2014Applicant: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Patent number: 8787065Abstract: Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.Type: GrantFiled: October 18, 2011Date of Patent: July 22, 2014Assignee: Micron Technology, Inc.Inventor: Alessandro Torsi
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Patent number: 8753919Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: GrantFiled: December 12, 2013Date of Patent: June 17, 2014Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Patent number: 8705290Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: GrantFiled: September 15, 2012Date of Patent: April 22, 2014Assignee: Micron Technology, Inc.Inventors: Prashant S. Damle, Krishna K. Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
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Publication number: 20140106533Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: ApplicationFiled: December 12, 2013Publication date: April 17, 2014Applicant: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Patent number: 8629421Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.Type: GrantFiled: October 15, 2012Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
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Publication number: 20130334483Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.Type: ApplicationFiled: June 14, 2012Publication date: December 19, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: D. V. Nirmal Ramaswamy, Sanh D. Tang, Alessandro Torsi, Muralikrishnan Balakrishnan, Xiaonan Chen, John K. Zahurak
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Patent number: 8610490Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: GrantFiled: March 25, 2013Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Patent number: 8565018Abstract: A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.Type: GrantFiled: June 1, 2012Date of Patent: October 22, 2013Assignee: Micron Technology, Inc.Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
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Patent number: 8451661Abstract: Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and applying a set of incrementing inhibit pulses to an unselected cell to fine-tune program the selected cell to a second threshold voltage.Type: GrantFiled: February 29, 2012Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Giuliano G. Imondi, Alessandro Torsi
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Publication number: 20130094276Abstract: Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: Micron Technology, Inc.Inventor: Alessandro Torsi
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Patent number: 8405444Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: GrantFiled: July 5, 2012Date of Patent: March 26, 2013Assignee: Micron Technology, Inc.Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Publication number: 20130016569Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.Type: ApplicationFiled: September 15, 2012Publication date: January 17, 2013Applicant: Micron Technology, Inc.Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda