Abstract: In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage, turning off an adjacent memory cell to the selected memory cell, and biasing remaining word lines on the source side of the turned-off memory cell with a Vlow voltage that is less than Vpass.

Abstract: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.

Abstract: A band gap voltage reference for an NMOS memory device includes a plurality of horizontal gate bipolar junction transistors that show improved gain at low collector currents. The horizontal gate bipolar transistors include an emitter formed by the NMOS memory device n+ source region, a base formed by the NMOS memory device p+ channel region, and a collector formed by the NMOS memory device n+ drain region, in which the base/channel region is less than 0.4 ?m in width and advantageously may be fabricated by standard flash memory manufacturing processes.

Abstract: A band gap voltage reference for an NMOS memory device includes a plurality of horizontal gate bipolar junction transistors that show improved gain at low collector currents. The horizontal gate bipolar transistors include an emitter formed by the NMOS memory device n+source region, a base formed by the NMOS memory device p+channel region, and a collector formed by the NMOS memory device n+drain region, in which the base/channel region is less than 0.4 ?m in width and advantageously may be fabricated by standard flash memory manufacturing processes.

Abstract: A band gap voltage reference for an NMOS memory device includes a plurality of horizontal gate bipolar junction transistors that show improved gain at low collector currents. The horizontal gate bipolar transistors include an emitter formed by the NMOS memory device n+ source region, a base formed by the NMOS memory device p+ channel region, and a collector formed by the NMOS memory device n+ drain region, in which the base/channel region is less than 0.4 &mgr;m in width and advantageously may be fabricated by standard flash memory manufacturing processes.

Abstract: A band gap voltage reference for an NMOS memory device includes a plurality of horizontal gate bipolar junction transistors that show improved gain at low collector currents. The horizontal gate bipolar transistors include an emitter formed by the NMOS memory device n+ source region, a base formed by the NMOS memory device p+ channel region, and a collector formed by the NMOS memory device n+ drain region, in which the base/channel region is less than 0.4 &mgr;m in width and advantageously may be fabricated by standard flash memory manufacturing processes.

Abstract: This invention relates to an improvement to an anisotropic chemical etching process for silicon oxide and to a manufacturing process for silicon FAMOS transistor Flash EPROM memory devices including said improvement, said silicon oxide chemical etching process having an etching direction and being characterised in that the following steps are performed:preliminary deposition of a layer of silicon nitride on the silicon oxide,a first anisotropic chemical etching or break-through stage, along said etching direction, aimed at removing the nitride layer from the silicon oxide surfaces orthogonal to said etching direction;a second anisotropic chemical etching stage along said etching direction, aimed at removing the silicon oxide surfaces orthogonal to said etching direction.