Patents by Inventor Alessandro Venca

Alessandro Venca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11012271
    Abstract: An RFID circuit and to a demodulator for an RFID circuit, the demodulator including an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite impulse response FIR filter arrangement connected to the input and connected to the comparator.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 18, 2021
    Assignee: EM Microelectronic-Marin SA
    Inventors: Alessandro Venca, Michel Moser
  • Publication number: 20190372808
    Abstract: An RFID circuit and to a demodulator for an RFID circuit, the demodulator including an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite impulse response FIR filter arrangement connected to the input and connected to the comparator.
    Type: Application
    Filed: May 13, 2019
    Publication date: December 5, 2019
    Applicant: EM Microelectronic-Marin SA
    Inventors: Alessandro VENCA, Michel MOSER
  • Patent number: 9954549
    Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 24, 2018
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Alessandro Venca, Claudio Nani, Nicola Ghittori, Alessandro Bosi
  • Publication number: 20170250702
    Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Inventors: Alessandro Venca, Claudio Nani, Nicola Ghittori, Alessandro Bosi
  • Patent number: 9660662
    Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 23, 2017
    Assignee: MARVELL WORLD TRADTE LTD.
    Inventors: Alessandro Venca, Claudio Nani, Nicola Ghittori, Alessandro Bosi
  • Patent number: 9654130
    Abstract: An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 16, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Alessandro Venca, Claudio Nani, Nicola Ghittori, Alessandro Bosi
  • Patent number: 9654132
    Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 16, 2017
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Alessandro Venca, Claudio Nani, Nicola Ghittori, Alessandro Bosi
  • Publication number: 20170012637
    Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 12, 2017
    Inventors: ALESSANDRO VENCA, CLAUDIO NANI, NICOLA GHITTORI, ALESSANDRO BOSI
  • Publication number: 20170012636
    Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 12, 2017
    Inventors: Alessandro Venca, Claudio Nani, Nicola Ghittori, Alessandro Bosi
  • Publication number: 20170012633
    Abstract: An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 12, 2017
    Inventors: Alessandro Venca, Claudio Nani, Nicola Ghittori, Alessandro Bosi
  • Patent number: 9258018
    Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: February 9, 2016
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Gregory Uehara, Chao Yang, Ruoxin Jiang, Fernando De Bernardinis, Alessandro Venca, Rinaldo Castello, Marc Leroux, Brian Brunn
  • Patent number: 9048783
    Abstract: In accordance with an embodiment of the disclosure, circuits and methods are provided for using a reconfigurable voltage controlled oscillator to support multi-mode applications. A voltage control oscillator circuit comprises a resonant circuit, a first oscillator circuitry coupled to the resonant circuit, and a second oscillator circuitry coupled to the resonant circuit. The voltage control oscillator circuit further comprises switching circuitry configured to select, based on an operating metric, one of the first oscillator circuitry and the second oscillator circuitry for providing an output voltage.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 2, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Antonio Liscidini, Luca Fanori, Rinaldo Castello, Alessandro Venca
  • Patent number: 9000815
    Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
  • Publication number: 20150038095
    Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Inventors: Gregory Uehara, Chao Yang, Ruoxin Jiang, Fernando De Bernardinis, Alessandro Venca, Rinaldo Castello, Marc Leroux, Brian Brunn
  • Patent number: 8896387
    Abstract: In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 25, 2014
    Assignee: Marvell International Ltd.
    Inventors: Alessandro Venca, Enrico Sacchi, Sehat Sutardja
  • Patent number: 8868015
    Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: October 21, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Gregory Uehara, Chao Yang, Ruoxin Jiang, Fernando De Bernardinis, Alessandro Venca, Rinaldo Castello, Marc Leroux, Brian Brunn
  • Patent number: 8400197
    Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: March 19, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
  • Publication number: 20120025880
    Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
    Type: Application
    Filed: July 26, 2011
    Publication date: February 2, 2012
    Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
  • Patent number: 8081039
    Abstract: In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: December 20, 2011
    Assignee: Marvell International Ltd.
    Inventors: Alessandro Venca, Enrico Sacchi, Sehat Sutardja
  • Patent number: 7880545
    Abstract: The present invention provides compensation for circuits. In one embodiment, a compensation circuit has a first terminal coupled to an output terminal of the circuit and a second terminal coupled to feed back the output voltage to an internal node. A damping circuit may also be coupled to the output terminal. The damping circuit adds a pole and a zero to the transfer function of the circuit. In one embodiment, the damping circuit modifies the effect of the output impedance of a load on the transfer function to increase the phase margin of the circuit such that the circuit remains stable over an increased range of output capacitor values.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: February 1, 2011
    Assignee: Marvell International Ltd.
    Inventors: Alessandro Venca, Daniele Ottini, Francesco Rezzi, Rinaldo Castello