Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (MOS) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. A first dielectric layer stack is arranged on the channel region, such that an orthogonal projection of the first dielectric layer stack on the main surface defining a first area is between and does not overlap the junctions and. A second dielectric layer stack is formed laterally adjacent to and in contact with the first dielectric layer stack, such that an orthogonal projection of the second dielectric layer stack overlaps the junction and defines a second area. A metal gate layer is formed on the first and second dielectric layer stacks, where an orthogonal projection of the metal gate layer on the main surface overlaps the first area and the second area.

Abstract: Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an over-reset state representing a logic value.

Abstract: A method for at least partially compensating for a change in threshold voltage level of a FET transistor induced by OFF-state stress degradation includes determining a signal indicative of a change in threshold voltage level of the FET with respect to a reference threshold voltage level, and applying a restoration signal to the FET. This restoration signal is adapted for shifting the threshold voltage level of the FET in a direction having opposite sign with respect to the change in threshold voltage level. Applying the restoration signal further includes taking into account the signal indicative of the change in threshold voltage level.

Abstract: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element.

Abstract: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.

Abstract: Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an over-reset state representing a logic value.

Abstract: Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an over-reset state representing a logic value.

Abstract: A method for tuning the effective work function of a gate structure in a semiconductor device is described. The semiconductor device is part of an integrated circuit and the gate structure has a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor device. The method includes providing an interconnect structure of the integrated circuit on top of the gate structure, the interconnect structure comprising a layer stack comprising at least a pre-metal dielectric layer comprising a metal filled connecting via connected to the gate structure through the pre-metal dielectric layer, and the interconnect structure having an upper exposed metal portion; and, thereafter, exposing at least a portion of the upper exposed metal portion to a plasma under predetermined exposure conditions, to tune the effective work function of the gate structure.

Abstract: A method for at least partially compensating for a change in threshold voltage level of a FET transistor induced by OFF-state stress degradation includes determining a signal indicative of a change in threshold voltage level of the FET with respect to a reference threshold voltage level, and applying a restoration signal to the FET. This restoration signal is adapted for shifting the threshold voltage level of the FET in a direction having opposite sign with respect to the change in threshold voltage level. Applying the restoration signal further includes taking into account the signal indicative of the change in threshold voltage level.

Abstract: A method for tuning the effective work function of a gate structure in a semiconductor device is described. The semiconductor device is part of an integrated circuit and the gate structure has a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor device. The method includes providing an interconnect structure of the integrated circuit on top of the gate structure, the interconnect structure comprising a layer stack comprising at least a pre-metal dielectric layer comprising a metal filled connecting via connected to the gate structure through the pre-metal dielectric layer, and the interconnect structure having an upper exposed metal portion; and, thereafter, exposing at least a portion of the upper exposed metal portion to a plasma under predetermined exposure conditions, to tune the effective work function of the gate structure.

Abstract: A method for operating a scanning probe microscope at elevated scan frequencies has a characterization stage of sweeping a plurality of excitation frequencies of the vertical displacement of the scanning element; measuring the value attained by the reading parameter at the excitation frequencies; and identifying plateau regions of the response spectrum of the reading parameter. The reading parameter variation is limited within a predetermined range over a predefined frequency interval, thereby defining corresponding fast scanning frequency windows in which the microscope assembly is sufficiently stable to yield a lateral resolution comparable to the one obtained during slow measurements. The measurement stage includes driving the scanning element along at least a scanning trajectory over the surface of the specimen at a frequency selected among the frequencies included in a fast scanning frequency window.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element.

Abstract: Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an over-reset state representing a logic value.

Abstract: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.

Abstract: Apparatus and methods determine a program verify (PV) induced reading parameter distribution. A measured post-PV reading parameter distribution can be compared with an expected post-PV reading parameter distribution. For example, de-convolution can be applied to identify the PV induced reading parameter distribution. Based on the PV-induced reading parameter distribution, adjustments can be made to one or more parameters of the PV process.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write or erase performance of a memory device.

Abstract: A method for operating a scanning probe microscope at elevated scan frequencies has a characterization stage of sweeping a plurality of excitation frequencies of the vertical displacement of the scanning element; measuring the value attained by the reading parameter at the excitation frequencies; and identifying plateau regions of the response spectrum of the reading parameter. The reading parameter variation is limited within a predetermined range over a predefined frequency interval, thereby defining corresponding fast scanning frequency windows in which the microscope assembly is sufficiently stable to yield a lateral resolution comparable to the one obtained during slow measurements. The measurement stage includes driving the scanning element along at least a scanning trajectory over the surface of the specimen at a frequency selected among the frequencies included in a fast scanning frequency window.