Patents by Inventor Alex J. Schrinsky
Alex J. Schrinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11877434Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.Type: GrantFiled: July 9, 2020Date of Patent: January 16, 2024Assignee: Micron Technology, Inc.Inventors: Yan Li, Song Guo, Mohd Kamran Akhtar, Alex J. Schrinsky
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Patent number: 11239242Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: GrantFiled: May 21, 2020Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Publication number: 20220013527Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Inventors: Yan Li, Song Guo, Mohd Kamran Akhtar, Alex J. Schrinsky
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Patent number: 11139309Abstract: Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed.Type: GrantFiled: July 3, 2019Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: Kamal Kumar Muthukrishnan, Alex J. Schrinsky
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Patent number: 11088147Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.Type: GrantFiled: June 26, 2019Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Jaydip Guha, Saurabh Keshav, Srinivas Pulugurtha, Mohd Kamran Akhtar, James B. Franek, Alex J. Schrinsky
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Publication number: 20210005619Abstract: Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Applicant: Micron Technology, Inc.Inventors: Kamal Kumar Muthukrishnan, Alex J. Schrinsky
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Publication number: 20200411529Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Inventors: Jaydip Guha, Saurabh Keshav, Srinivas Pulugurtha, Mohd Kamran Akhtar, James B. Franek, Alex J. Schrinsky
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Publication number: 20200286898Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Applicant: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Publication number: 20200243537Abstract: Methods, apparatuses, and systems related to forming a trench using a polymerizing radical material. An example method includes depositing a polymerizing radical material in a number of trenches formed over a substrate. The method further includes etching a portion of the deposited polymerizing radical material from the number of trenches. The example method further includes selectively etching into one of the number of trenches below the deposited polymerizing radical material. The one of the number of trenches is narrower than another of the number of trenches.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Inventors: Yan Li, Song Guo, Mohd Kamran Akhtar, Alex J. Schrinsky
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Patent number: 10700073Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: GrantFiled: May 22, 2019Date of Patent: June 30, 2020Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Publication number: 20190378843Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: ApplicationFiled: May 22, 2019Publication date: December 12, 2019Applicant: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Patent number: 10347643Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.Type: GrantFiled: June 7, 2018Date of Patent: July 9, 2019Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
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Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
Patent number: 10134741Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: GrantFiled: July 18, 2017Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Methods Of Forming An Elevationally Extending Conductor Laterally Between A Pair Of Conductive Lines
Publication number: 20180019245Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: ApplicationFiled: July 18, 2017Publication date: January 18, 2018Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
Patent number: 9754946Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: GrantFiled: July 14, 2016Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Patent number: 9679964Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.Type: GrantFiled: September 14, 2015Date of Patent: June 13, 2017Assignee: Micron Technologies, Inc.Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew J. King
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Patent number: 9330934Abstract: Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.Type: GrantFiled: May 18, 2009Date of Patent: May 3, 2016Assignee: Micron Technology, Inc.Inventors: Baosuo Zhou, Alex J. Schrinsky
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Publication number: 20160005815Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Applicant: Micron Technology, Inc.Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew J. King
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Publication number: 20150340611Abstract: Various embodiments of the present invention are directed to a method for fabricating a memory cell comprising performing a passivation step on a cell structure and cell source lines prior to exhuming a masking layer to prevent oxidation of the cell structure and source lines.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Applicant: Sony CorporationInventors: Kamran Akhtar, Ashim Dutta, Alex J. Schrinsky, Shane J. Trapp
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Patent number: 9136331Abstract: Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.Type: GrantFiled: April 10, 2013Date of Patent: September 15, 2015Assignee: Micron Technology, Inc.Inventors: Chris Larsen, Alex J. Schrinsky, John D. Hopkins, Matthew King