Abstract: Various exemplary embodiments relate to a brace for use with an integrated circuit (IC), and to an IC package with a brace, having a main body portion and a fastening portion for mechanically fastening the main body portion to the IC, by for example clipping or sliding attachment. Other exemplary embodiments relate to a method of stabilizing an IC during an operation carried out on the IC, such as a soldering operation, involving for example steps of attaching a brace to the IC, performing the operation on the IC, and/or removing the brace after performing the operation.

Abstract: An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments, the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.

Abstract: An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of a layer of material bonded to the top of the integrated circuit package. The layer of material may have a generally planar-convex or a generally planar-concave cross-section. By appropriate choice of temperature coefficient and degree of concavity or convexity, the layer of material can compensate for either convex or concave warpage. In some embodiments the layer of material has apertures therein allowing compensation for more complex warpages. The apparatus provides an alternative to apparatus for dealing with IC package warpage known in the art.

Abstract: An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.

Abstract: Various exemplary embodiments relate to a stiffener for use with and integrated circuit (IC). The stiffener can be attached to the IC, and can utilize a planar portion and one or more beam portions that project from the planar portion at a non-zero angle. The stiffener can alternatively include a frame formed of beam portions that are adjacent the sides of the IC. The stiffener can provide added stiffness to the IC package to resist warping of the IC during soldering.

Abstract: Various exemplary embodiments relate to a brace for use with an integrated circuit (IC), and to an IC package with a brace, having a main body portion and a fastening portion for mechanically fastening the main body portion to the IC, by for example clipping or sliding attachment. Other exemplary embodiments relate to a method of stabilizing an IC during an operation carried out on the IC, such as a soldering operation, involving for example steps of attaching a brace to the IC, performing the operation on the IC, and/or removing the brace after performing the operation.

Abstract: A solution for mounting decoupling capacitors on a printed wiring board (PWB) used for mounting a high performance ball grid array (BGA) device is described. The via array that connects the BGA device is modified, the modification being that at least a portion of one row of said vias array is missing at least two adjacent vias. The missing vias are replaced by respective shared vias in an adjacent row, and the shared vias are connected to either a power supply or a power return. The shared vias are also provided with via pads on the other side of said PWB, and a decoupling capacitor can be electrically connected across the pair of via pads to decouple the power supply and the power return at the two adjacent vias.

Abstract: A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating, elongating and/or truncating the selected adjacent pairs and rotating their respective corresponding via pairs to adapt the spacing between the selected adjacent via pairs in the BGA land pattern and applying the capacitor pads to the selected via pairs. The selected adjacent via pairs and their respective link connectors are rotated, elongated and/or truncated in mutually opposite directions.