Patents by Inventor ALEXANDER FRITSCH
ALEXANDER FRITSCH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11664068Abstract: A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.Type: GrantFiled: July 5, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Rajiv Joshi, Sudipto Chakraborty, Alexander Fritsch, Holger Wetter
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Publication number: 20230005521Abstract: A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.Type: ApplicationFiled: July 5, 2021Publication date: January 5, 2023Inventors: Rajiv Joshi, Sudipto Chakraborty, Alexander Fritsch, Holger Wetter
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Patent number: 11527283Abstract: A sense amplifier circuit includes a bitline node, a sense node, and a feedback circuit which is connected to the bitline node and to the sense node. The feedback circuit includes a cascode-connected pair of transistors configured to isolate the bitline node from an occurrence of a voltage variation on the sense node.Type: GrantFiled: January 15, 2021Date of Patent: December 13, 2022Assignee: International Business Machines CorporationInventors: Sudipto Chakraborty, Rajiv Joshi, Alexander Fritsch, Holger Wetter
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Publication number: 20220230678Abstract: A sense amplifier circuit includes a bitline node, a sense node, and a feedback circuit which is connected to the bitline node and to the sense node. The feedback circuit includes a cascode-connected pair of transistors configured to isolate the bitline node from an occurrence of a voltage variation on the sense node.Type: ApplicationFiled: January 15, 2021Publication date: July 21, 2022Inventors: Sudipto Chakraborty, Rajiv Joshi, Alexander Fritsch, Holger Wetter
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Patent number: 10984160Abstract: Circuit analysis and modification by receiving a first description of a circuit, the first description having a first level of detail, receiving a second description of the circuit, the second description having a second level of detail, performing a circuit simulation according to the first description, identifying an active node of the first description according to the simulation, and modifying the second description according to the active node.Type: GrantFiled: May 7, 2020Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Martin Bernhard Schmidt, Alexander Fritsch, Werner Juchmes, Simon Brandl
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Patent number: 10832763Abstract: Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.Type: GrantFiled: December 18, 2018Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Bernhard Schmidt, Harry Barowski, Alexander Fritsch, Matthias Hock
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Publication number: 20200194060Abstract: Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.Type: ApplicationFiled: December 18, 2018Publication date: June 18, 2020Inventors: Martin Bernhard Schmidt, Harry Barowski, Alexander Fritsch, Matthias Hock
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Patent number: 10614884Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.Type: GrantFiled: March 8, 2019Date of Patent: April 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Alexander Fritsch
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Patent number: 10529388Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: GrantFiled: August 29, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 10347337Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.Type: GrantFiled: December 7, 2017Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Alexander Fritsch
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Publication number: 20190206492Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Inventors: Martin ECKERT, Alexander FRITSCH
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Publication number: 20180374517Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: ApplicationFiled: August 29, 2018Publication date: December 27, 2018Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 10096346Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: GrantFiled: July 19, 2017Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20180204618Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.Type: ApplicationFiled: December 7, 2017Publication date: July 19, 2018Inventors: Martin ECKERT, Alexander FRITSCH
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Patent number: 10002661Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: GrantFiled: May 5, 2017Date of Patent: June 19, 2018Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Patent number: 9892789Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.Type: GrantFiled: January 16, 2017Date of Patent: February 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Alexander Fritsch
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Publication number: 20170316812Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 9767872Abstract: An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: GrantFiled: July 28, 2016Date of Patent: September 19, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Patent number: 9761286Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.Type: GrantFiled: August 24, 2016Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20170243633Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: ApplicationFiled: May 5, 2017Publication date: August 24, 2017Inventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel