Patents by Inventor ALEXANDER FRITSCH
ALEXANDER FRITSCH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9727680Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: GrantFiled: May 16, 2016Date of Patent: August 8, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Patent number: 9721050Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: GrantFiled: May 16, 2016Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Patent number: 9721049Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: GrantFiled: May 16, 2016Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Patent number: 9666278Abstract: A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells.Type: GrantFiled: September 16, 2015Date of Patent: May 30, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Werner Juchmes, Shankar Kalyanasundaram, Rolf Sautter
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Publication number: 20170084314Abstract: Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.Type: ApplicationFiled: September 17, 2015Publication date: March 23, 2017Inventors: Alexander Fritsch, Shankar Kalyanasundaram, Michael Kugel, Juergen Pille
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Patent number: 9595304Abstract: The invention relates to a current sense amplifier (103) comprising a reference current input terminal (109), a sense control line input terminal (125), a sense current input terminal (108), a first output terminal (106), and a second output terminal (107).Type: GrantFiled: December 4, 2015Date of Patent: March 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Ulrich Krauch, Michael B. Kugel, Juergen Pille
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Patent number: 9589604Abstract: Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.Type: GrantFiled: September 17, 2015Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Shankar Kalyanasundaram, Michael Kugel, Juergen Pille
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Publication number: 20170047111Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: ApplicationFiled: May 16, 2016Publication date: February 16, 2017Inventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Publication number: 20170047112Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: ApplicationFiled: May 16, 2016Publication date: February 16, 2017Inventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Publication number: 20170046465Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: ApplicationFiled: May 16, 2016Publication date: February 16, 2017Inventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Patent number: 9564188Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: GrantFiled: August 31, 2015Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Patent number: 9552851Abstract: A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.Type: GrantFiled: August 31, 2015Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 9536608Abstract: Disclosed aspects include a content addressable memory device comprising at least two memory banks connectable to a global search line. Each memory bank comprises at least two content addressable memory cells. Each content addressable memory cell can store one bit. Each content addressable memory cell is coupled to a respective local search line. Aspects include a bank connection circuitry configured for coupling the global search line to the local search lines in dependence of a bank prediction signal line. The bank connection circuitry of the content addressable memory device may comprise bank hold circuitry for storing a search value transmitted by the global search line.Type: GrantFiled: November 17, 2015Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Amira Rozenfeld, Gordon B. Sapp, Rolf Sautter
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Publication number: 20160365130Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20160336049Abstract: An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Patent number: 9484073Abstract: The invention relates to a current sense amplifier. The current sense amplifier comprises: a first NAND gate comprising an output terminal being connected to a first output terminal, a second NAND gate comprising an output terminal being connected to a second output terminal, a first cross coupled inverter, and a second cross coupled inverter, the first inverter comprising a first n-FET and the second inverter comprising a second n-FET, a transmission gate comprising a first and a second transmission terminal and a transmission control terminal, the transmission control terminal being connected to a sense control line input terminal, a third n-FET having a source connected to a sense current input terminal and a drain connected to a source of the first n-FET, a fourth n-FET having a source connected to a reference current input terminal and a drain connected to a source of the second n-FET.Type: GrantFiled: December 15, 2015Date of Patent: November 1, 2016Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Iris M. Leefken, Rolf Sautter
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Patent number: 9431096Abstract: A memory device having a plurality of banks of memory cells may be provided. Each memory cells may be interconnected via a local write bit-line and a complementary local write bit-line to a local write bit-line buffer circuit. The local write bit-line buffer circuit may be connected via a global write bit-line and a complementary one to a negative bias write assist circuit. The memory device may also comprise an address decoder separately connected to the local write bit-line buffer circuits. The address decoder may comprise a generating unit for enabling exactly one local write enable signal for a respective one of said local write bit-line buffer circuits. The local write bit-line buffer circuit may be adapted for generating local write data on said local write bit-line in response to receiving global write data on said global write bit-line when its local write enable signal is enabled.Type: GrantFiled: November 17, 2015Date of Patent: August 30, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Werner Juchmes, Michael B. Kugel, Rolf Sautter
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Patent number: 9431098Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.Type: GrantFiled: August 10, 2015Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Amira Rozenfeld, Rolf Sautter, Dieter Wendel
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Publication number: 20160099053Abstract: A memory apparatus includes a content addressable memory, CAM, cell block including CAM cells and a random access memory (RAM), cell block including RAM cells. A geometric footprint of each of the CAM cells has a side bigger than a side of a geometric footprint of each of the RAM cells, where the sides of the CAM cells and the RAM cells are parallel to each other. The apparatus is configured to translate an input keyword at an input of the CAM cell block to an output word at an output of the RAM cell block when the keyword at the input of the CAM cell block is stored in the CAM cell block. The CAM cell block is split into a first part and a second part of the CAM cells.Type: ApplicationFiled: September 16, 2015Publication date: April 7, 2016Inventors: Alexander Fritsch, Werner Juchmes, Shankar Kalyanasundaram, Rolf Sautter
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Publication number: 20160071555Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: ApplicationFiled: August 31, 2015Publication date: March 10, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter