Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract: The present invention is directed to the combination therapy of an afucosylated anti-CD20 antibody with fludarabine and/or mitoxantrone for the treatment of cancer, especially to the combination therapy of CD20 expressing cancers with an afucosylated humanized B-Ly1 antibody with fludarabine and/or mitoxantrone.

Abstract: A method of manufacturing semiconductor modules includes providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer, attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil, and encasing the semiconductor dies attached to the metal foil in an electrically insulating material. The metal layer and the metal foil are structured after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer. The electrically insulating material is divided along the surface regions devoid of the metal foil and the metal layer to form individual modules.

Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.

Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A backing piece for attaching an electrical component to a housing wall of an electrical household appliance and arrangement behind a matching opening in the housing wall includes a body having an essentially rectangular base surface, and a peripheral web configured as an elastic sealing lip for support against a rear face of the housing wall. Holding elements project from the body and form with the sealing lip a gap which receives a section of the housing wall at an edge of the opening. The holding elements are arranged in spaced-apart relationship about a periphery of the body such that at least one of the holding element is arranged on each of four sides of the rectangular base surface and one of the holding elements is provided at each of the corners of the body so as to apply a pressing force sufficient upon each section of the sealing lip.

Abstract: The present invention is directed to the combination therapy of an afucosylated anti-CD20 antibody with fludarabine and/or mitoxantrone for the treatment of cancer, especially to the combination therapy of CD20 expressing cancers with an afucosylated humanized B-Ly1 antibody with fludarabine and/or mitoxantrone.

Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A method for operating an exhaust gas system for an internal combustion engine, in which the exhaust gas system includes at least one first catalytic coating and at least one second catalytic coating, the second catalytic coating being situated in the exhaust gas flow downstream from the first catalytic coating. An additional quantity of hydrocarbons is occasionally introduced into the exhaust gas upstream from the first catalytic coating so that a heat-generating reaction may take place in the second catalytic coating. With the aid of at least one temperature sensor and/or at least one hydrocarbon sensor and/or at least one lambda sensor upstream and/or downstream from the second catalytic coating, at least one property of the exhaust gas is ascertained which characterizes a reaction of the second catalytic coating due to the additional quantity of hydrocarbons.

Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.

Abstract: An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of semiconductor chips is placed over a carrier with the electrically conductive particles facing the carrier. The electrically conductive particles are heated until the at least one semiconductor chip adheres to the carrier.

Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Abstract: A method for access or starting verification for a vehicle using a mobile identification encoder and at least two antennas located in or on the vehicle at different locations includes: the antennas emitting electromagnetic signals at alterable times, wherein the electromagnetic signals are emitted in transmission blocks having alterable specific properties and wherein a plurality of transmission blocks are strung together to form a communication message in which each transmission block adopts an alterable position in time, the identification encoder receiving the electromagnetic signals emitted by the antennas and processing them to generate a response signal, and altering at least one of the times at which the individual antennas are actuated, the specific properties of the individual transmission blocks, and the position of the individual transmission blocks in time in the communication message in accordance with a cryptographical method.

Abstract: A method for operating an exhaust gas system for an internal combustion engine, in which the exhaust gas system includes at least one first catalytic coating and at least one second catalytic coating, the second catalytic coating being situated in the exhaust gas flow downstream from the first catalytic coating. An additional quantity of hydrocarbons is occasionally introduced into the exhaust gas upstream from the first catalytic coating so that a heat-generating reaction may take place in the second catalytic coating. With the aid of at least one temperature sensor and/or at least one hydrocarbon sensor and/or at least one lambda sensor upstream and/or downstream from the second catalytic coating, at least one property of the exhaust gas is ascertained which characterizes a reaction of the second catalytic coating due to the additional quantity of hydrocarbons.