Patents by Inventor Alexander Kotov
Alexander Kotov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10660657Abstract: A bone material removal device, including a tubular element comprising a proximal end and a distal end, a shaft received within the tubular element and comprising a proximal end and a distal end, a cutting tooth movably coupled to the distal end of the shaft and a shaft displacement actuator at the proximal end of the tubular element rotatably coupled to the shaft, wherein at least partial rotation of the actuator in a first direction brings the cutting tooth to travel from a closed retracted position to an open extended position.Type: GrantFiled: August 9, 2018Date of Patent: May 26, 2020Assignee: T.A.G. Medical Devices—Agriculture Cooperative Ltd.Inventors: Leon Slobitker, Alexander Kotov, Aviram Alfia, Dima Gurevich, Roy Zilberman, Hagay Sitry, Hagay Botansky, Dror Biton
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Publication number: 20200066738Abstract: A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.Type: ApplicationFiled: December 4, 2018Publication date: February 27, 2020Inventors: Yuri Tkachev, Alexander Kotov, Nhan Do
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Publication number: 20200065023Abstract: A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region. Control circuitry is configured to, for one of the memory cells, apply a first pulse of programming voltages that includes a first voltage applied to the control gate, perform a read operation that includes detecting currents through the channel region for different control gate voltages to determine a target control gate voltage using the detected currents that corresponds to a target current through the channel region, and apply a second pulse of programming voltages that includes a second voltage applied to the control gate that is determined from the first voltage, a nominal read voltage and the target voltage.Type: ApplicationFiled: December 12, 2018Publication date: February 27, 2020Inventors: Viktor Markov, Alexander Kotov
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Publication number: 20190388102Abstract: A bone material removal device including a cannula, a bone drilling forward tip and a bore widening element including a bone carving portion that slides axially relative to the cannula and extends in a circumferential direction and wherein the axial movement of the bore widening element relative to the cannula brings a carving portions to travel and extend radially in a circumferential direction beyond a surface of the cannula and carve bone from a wall of a bore.Type: ApplicationFiled: September 5, 2019Publication date: December 26, 2019Applicant: T.A.G. Medical Devices - Agriculture Cooperative Ltd.Inventors: Leon SLOBITKER, Hagay SITRY, Alexander KOTOV, Ran WEISMAN
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Patent number: 10448959Abstract: A bone material removal device including a cannula, a bone drilling forward tip and a bore widening element including a bone carving portion that slides axially relative to the cannula and extends in a circumferential direction and wherein the axial movement of the bore widening element relative to the cannula brings a carving portions to travel and extend radially in a circumferential direction beyond a surface of the cannula and carve bone from a wall of a bore.Type: GrantFiled: April 7, 2016Date of Patent: October 22, 2019Assignee: T.A.G. Medical Devices—Agriculture Cooperative Ltd.Inventors: Leon Slobitker, Hagay Sitry, Alexander Kotov, Ran Weisman
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Publication number: 20180360467Abstract: A bone material removal device, including a tubular element comprising a proximal end and a distal end, a shaft received within the tubular element and comprising a proximal end and a distal end, a cutting tooth movably coupled to the distal end of the shaft and a shaft displacement actuator at the proximal end of the tubular element rotatably coupled to the shaft, wherein at least partial rotation of the actuator in a first direction brings the cutting tooth to travel from a closed retracted position to an open extended position.Type: ApplicationFiled: August 9, 2018Publication date: December 20, 2018Inventors: Leon Slobitker, Alexander Kotov, Aviram Alfia, Dima Gurevich, Roy Zilberman, Hagay Sitry, Hagay Botansky, Dror Biton
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Patent number: 10079061Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.Type: GrantFiled: March 30, 2016Date of Patent: September 18, 2018Assignee: SILICON STORAGE TECHNOLOGY, INC.Inventors: Xiaozhou Qian, Viktor Markov, Jong-Won Yoo, Xiao Yan Pi, Alexander Kotov
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Publication number: 20170128086Abstract: A bone material removal device including a cannula, a bone drilling forward tip and a bore widening element including a bone carving portion that slides axially relative to the cannula and extends in a circumferential direction and wherein the axial movement of the bore widening element relative to the cannula brings a carving portions to travel and extend radially in a circumferential direction beyond a surface of the cannula and carve bone from a wall of a bore.Type: ApplicationFiled: April 7, 2016Publication date: May 11, 2017Inventors: Leon SLOBITKER, Hagay SITRY, Alexander KOTOV, Ran WEISMAN
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Publication number: 20160336072Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.Type: ApplicationFiled: March 30, 2016Publication date: November 17, 2016Inventors: Xiaozhou Qian, Viktor Markov, Jong-Won Yoo, Xiao Yan Pi, Alexander Kotov
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Patent number: 9431126Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.Type: GrantFiled: March 14, 2014Date of Patent: August 30, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, James Cheng, Dmitry Bavinov, Alexander Kotov, Jong-Won Yoo
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Patent number: 9293217Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.Type: GrantFiled: March 14, 2014Date of Patent: March 22, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, James Cheng, Dmitry Bavinov, Alexander Kotov, Jong-Won Yoo
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Patent number: 9275748Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.Type: GrantFiled: February 25, 2014Date of Patent: March 1, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Nhan Do, Steven Malcolm Lemke, Jinho Kim, Jong-Won Yoo, Alexander Kotov, Yuri Tkachev
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Patent number: 9123431Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.Type: GrantFiled: March 14, 2014Date of Patent: September 1, 2015Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, James Cheng, Dmitry Bavinov, Alexander Kotov, Jong-Won Yoo
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Patent number: 9123822Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.Type: GrantFiled: August 2, 2013Date of Patent: September 1, 2015Assignee: Silicon Storage Technology, Inc.Inventors: Jong-Won Yoo, Alexander Kotov, Yuri Tkachev, Chien-Sheng Su
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Publication number: 20150035040Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Inventors: Jong-Won Yoo, Alexander Kotov, Yuri Tkachev, Chien-Sheng Su
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Patent number: 8883592Abstract: A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.Type: GrantFiled: July 26, 2012Date of Patent: November 11, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Alexander Kotov, Chien-Sheng Su
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Publication number: 20140269062Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.Type: ApplicationFiled: February 25, 2014Publication date: September 18, 2014Applicant: Silicon Storage Technology, Inc.Inventors: Nhan Do, Steven Malcolm Lemke, Jinho Kim, Jong-Won Yoo, Alexander Kotov, Yuri Tkachev
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Publication number: 20140269058Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Silicon Storage Technology, Inc.Inventors: Xian Liu, James Cheng, Dmitry Bavinov, Alexander Kotov, Jong-Won Yoo
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Patent number: 8780639Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: GrantFiled: May 8, 2012Date of Patent: July 15, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20140104961Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: May 8, 2012Publication date: April 17, 2014Applicant: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu