Abstract: Methods and systems for processing a video signal are disclosed herein. Pixels may be interpolated utilizing at most two passes. During a first of the two passes, an aligned sub-pixel value may be interpolated utilizing a plurality of integer pixel values, if the aligned sub-pixel value is horizontally or vertically aligned with the plurality of integer pixel values. During a second of the two passes, a non-aligned sub-pixel value may be interpolated utilizing the interpolated aligned sub-pixel value, if the non-aligned sub-pixel value is not horizontally or vertically aligned with the plurality of integer pixel values. The aligned sub-pixel value may be interpolated utilizing 4-tap filtering of the integer pixel values.

Abstract: In a data processing system, a method and system for codifying signals that ensure high fidelity reconstruction are provided. A minimum number of most significant bits (MSBs) may be determined for use in a two-dimensional (2D) transform matrix during forward and inverse transform operations so that high fidelity reconstruction may be possible without the need for mismatch error control. For a forward transform operation, a minimum number of F MSBs may be selected from a reference transform coefficient in an effective transform matrix to ensure high fidelity reconstruction. For an inverse transform operation, a minimum number of R MSBs may be selected from the reference transform coefficient in the effective transform matrix to ensure high fidelity reconstruction. The effective transform matrix may result from the decomposition and implementation of a finite precision transform matrix. At least one dimension of the transform matrix may comprise four or eight points.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Abstract: A system and method that support both progressive and interlaced format video transmission and display. The system utilizes de-interlacing techniques to convert input interlaced format video to progressive format video, and compress and vertically scale the progressive format video to communicate videos more efficiently in a progressive format. The system also supports interlaced and progressive displays, where after decompressing and vertically resealing the communicated compressed progressive format video, the video may be converted to interlaced format if the display supports interlaced format video. The system is capable of dynamically switching between the progressive and the interlaced format modes.

Abstract: Presented herein are a system, method, and apparatus for improving scaling with early deinterlacing. Interlaced frames are deinterlaced prior to scaling. Accordingly, the scaler scales an entire frame, in contrast to individual fields, thereby resulting in an improved scaling function.

Abstract: System(s) and method(s) for a video data cache are presented herein. During decoding, the video decoder fetches portions of a reference frame. The video data cache is first checked for the portions of the reference frame. If the portion of the reference frame is found in the video data cache, the portion is fetched from the video data cache. The foregoing avoids a DRAM fetch and cycles associated with the DRAM fetch.

Abstract: Certain embodiments of the invention provide a method and apparatus for DRAM 2D video word formatting. In one aspect of the invention, words of data in a DRAM may be arranged for optimal DRAM operating efficiency. The data organization may utilize a 2-dimensional array of samples, for example. In one embodiment of the invention, a 128-bit or 16-byte word or GWord of DRAM may include an 8×2 array of luma samples, comprising 8 horizontal samples and 2 vertical samples from one field, for example. In this regard, either both may be even lines or both may be odd lines. Various other 2-dimensional arrangements may be chosen according to the demands of the video format being processed in accordance with various embodiments of the invention.

Abstract: A system, method, and apparatus for guiding a deinterlacer are presented herein. The deinterlacer is provided a deinterlacing coefficient which the deinterlacer uses to select a deinterlacing scheme which best utilizes system resources. The deinterlacing coefficient is calculated based on the various attributes associated with a macroblock of an interlaced field, such as motion vectors. Because the attributes are calculated and encoded prior to transmission of the macroblock over a communication channel, generation of the deinterlacing coefficient does not require significant additional computation resources.

Abstract: A system and method for decoding digital video by processing multiple regions of an image in parallel, even when there are dependencies between rows in the image, are disclosed. The method generally involves decoding multiple rows concurrently, with the start of decoding of a given row being delayed until portions of the other rows on which the given row depends have been decoded. The system generally comprises parallel processors, with one processor typically decoding one row and another processor typically decoding the row above it. In accordance with the present invention, however, any number or type of processors can decode, or perform decoding functions on, the image in parallel.