Abstract: Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.

Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Abstract: Flash memory devices and methods for fabricating the same are provided. A method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a P-type silicon substrate and implanting an impurity dopant into the substrate substantially between the first gate stack and the second gate stack to form an impurity-doped region of the substrate. A channel region underlies the first gate stack adjacent to the impurity-doped region. An intrinsically tensile-stressed insulating member is formed between the first and the second gate stacks and overlying the impurity-doped region. The tensile-stressed insulating member causes a uniaxial lateral tensile stress to be transmitted to the first channel region. A word line is formed overlying the intrinsically tensile-stressed insulating member and in electrical contact with the first gate stack and the second gate stack.

Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.

Abstract: Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

Abstract: A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.

Abstract: A memory element includes a first electrode, a passive layer on and in contact with the first electrode, a polyfluorene active layer on and in contact with the active layer, and a second electrode on and in contact with the polyfluorene active layer. The chemical structure of the polyfluorene active layer may be altered to take different forms, each providing a different memory element operating characteristic.