Patents by Inventor Alexander Philippou
Alexander Philippou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10304952Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.Type: GrantFiled: May 25, 2018Date of Patent: May 28, 2019Assignee: Infineon Technologies AGInventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
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Publication number: 20190123185Abstract: A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.Type: ApplicationFiled: October 23, 2018Publication date: April 25, 2019Inventors: Antonio Vellei, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Publication number: 20190123186Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.Type: ApplicationFiled: October 23, 2018Publication date: April 25, 2019Inventors: Alexander Philippou, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
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Patent number: 10256299Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.Type: GrantFiled: August 14, 2017Date of Patent: April 9, 2019Assignee: Infineon Technologies AGInventors: Alexander Philippou, Anton Mauder
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Publication number: 20180342605Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.Type: ApplicationFiled: May 25, 2018Publication date: November 29, 2018Inventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
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Patent number: 10109624Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.Type: GrantFiled: April 20, 2017Date of Patent: October 23, 2018Assignee: Infineon Technologies AGInventors: Markus Bina, Franz-Josef Niedernostheide, Alexander Philippou
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Patent number: 10096531Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region.Type: GrantFiled: September 22, 2015Date of Patent: October 9, 2018Assignee: Infineon Technologies AGInventors: Christian Jaeger, Johannes Georg Laven, Frank Dieter Pfirsch, Alexander Philippou
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Publication number: 20180286971Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.Type: ApplicationFiled: March 29, 2018Publication date: October 4, 2018Inventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Antonio Vellei
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Publication number: 20180076309Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.Type: ApplicationFiled: September 14, 2017Publication date: March 15, 2018Applicant: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
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Publication number: 20180053822Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.Type: ApplicationFiled: August 14, 2017Publication date: February 22, 2018Inventors: Alexander Philippou, Anton Mauder
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Publication number: 20180033705Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.Type: ApplicationFiled: July 24, 2017Publication date: February 1, 2018Inventors: Alexander Philippou, Erich Griebl, Johannes Georg Laven, Maria Cotorogea
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Publication number: 20170309619Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.Type: ApplicationFiled: April 20, 2017Publication date: October 26, 2017Applicant: Infineon Technologies AGInventors: Markus Bina, Franz-Josef Niedernostheide, Alexander Philippou
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Patent number: 9691887Abstract: A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device.Type: GrantFiled: September 17, 2015Date of Patent: June 27, 2017Assignee: Infineon Technologies AGInventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Frank Dieter Pfirsch
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Patent number: 9653568Abstract: A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.Type: GrantFiled: June 9, 2015Date of Patent: May 16, 2017Assignee: Infineon Technologies AGInventors: Johannes Georg Laven, Alexander Philippou, Hans-Joachim Schulze, Christian Jaeger, Roman Baburske, Antonio Vellei
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Patent number: 9553179Abstract: A semiconductor device includes a semiconductor mesa which is formed between cell trench structures extending from a first surface into a semiconductor body. The semiconductor mesa includes a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface. Source zones are arranged along a longitudinal axis of the semiconductor mesa at a first distance from each other and form second pn junctions with the body zone. A barrier structure, which has the conductivity type of the source zones, forms at least one of a unipolar homojunction with the drift zone and a pn junction with the body zone at least outside a vertical projection of the source zones perpendicular to the first surface. The barrier structure may be absent in the vertical projection of the source zones.Type: GrantFiled: January 31, 2014Date of Patent: January 24, 2017Assignee: Infineon Technologies AGInventors: Antonio Vellei, Johannes Georg Laven, Roman Baburske, Alexander Philippou
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Publication number: 20160099188Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region.Type: ApplicationFiled: September 22, 2015Publication date: April 7, 2016Inventors: Christian Jaeger, Johannes Georg Laven, Frank Dieter Pfirsch, Alexander Philippou
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Publication number: 20160087005Abstract: A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device.Type: ApplicationFiled: September 17, 2015Publication date: March 24, 2016Inventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Frank Dieter Pfirsch
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Publication number: 20150279985Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: Alexander Philippou, Johannes Georg Laven, Christian Jaeger, Frank Wolter, Frank Pfirsch, Antonio Vellei
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Publication number: 20150270369Abstract: A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.Type: ApplicationFiled: June 9, 2015Publication date: September 24, 2015Inventors: Johannes Georg Laven, Alexander Philippou, Hans-Joachim Schulze, Christian Jaeger, Roman Baburske, Antonio Vellei
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Publication number: 20150221756Abstract: A semiconductor device includes a semiconductor mesa which is formed between cell trench structures extending from a first surface into a semiconductor body. The semiconductor mesa includes a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface. Source zones are arranged along a longitudinal axis of the semiconductor mesa at a first distance from each other and form second pn junctions with the body zone. A barrier structure, which has the conductivity type of the source zones, forms at least one of a unipolar homojunction with the drift zone and a pn junction with the body zone at least outside a vertical projection of the source zones perpendicular to the first surface. The barrier structure may be absent in the vertical projection of the source zones.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Inventors: Antonio Vellei, Johannes Georg Laven, Roman Baburske, Alexander Philippou