Abstract: A processing architecture for performing a plurality of tasks comprises a conveyor of pipe stages, having a certain width comprising different fields including commands and operands, and a clock signal; wherein each pipe stage performs a certain part of an operation for each task of the plurality in a respective time slot.

Abstract: A method for producing a probe unit for contacting an electronic circuit such as a wafer or a die having a predetermined pattern of contact pads deployed in a common plane. The method employes a base plate of made of a material capable of surface uplift when irradiated. On the surface of the base plate locations corresponding to said contact pads are determined. Further, the base plate is irradiated at the determined locations by means of a laser. This results in forming conical surface uplifts. The method further includes plating the conical surface uplifts with an electrically conductive material and providing means for electical connection between said plated conical surface uplifts and an external device.

Abstract: An adaptive equaliser comprises a variable filter, means for measuring a received signal and control means for adjusting the filter parameters, wherein the filter parameters are adjusted based on the width of the eye opening measured in the eye diagram of the received signal. The received signal is scanned at a variable voltage or current threshold to construct a digitised representation. This information is applied to establish the correct coefficients in an equalisation filter that compensates for the distortion of the channel. The filter may be arranged in the receiver, in the transmitter, or both in the transmitter and the receiver.

Abstract: The present invention relates to the reduction of timing uncertainty in high speed communications channel or interface and to a receiver and method using the same. The receiver according to the invention comprises a plurality of samplers for latching data. The invention provides improvements to the Bit Error rate versus channel and inherent register noise, as a result of employment of the characteristic of phase noise within the receiving registers to measure the characteristics of the channel and to compensate for variations in the channel by altering the timing characteristics of the signal.

Abstract: The present invention relates in general to the field of generation of precise electrical signals, in particular, to a technique for providing accurate delays of signals using a controllable delay line, and is applicable to the areas of high speed communication and memory testing equipment. According to the present invention, an auxiliary reference channel having a delay line which is identical to the main delay line is incorporated into vernier silicon die to allow automatic adjustment of the delay in the main delay line using a reference periodical signal applied to the auxiliary delay line.

Abstract: The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips. A data transmission means for high-speed transmission of digital data is proposed, the data transmission means comprising: at least one driver for driving a transmission line; and a timing deskewing means connected thereto, wherein the timing deskewing means comprises a storage means for recording and storing information on skew caused by inter-symbol interference and cross-talk influence in the transmission line, for at least one data pattern transmitted through the transmission line; and an adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate for the above skew.

Abstract: Automatic test equipment for memory device testing provides continuous high-speed testing by intelligent pausing a timer when a buffer memory is full or nearly full, the timer being paused is capable of properly maintaining refresh and clock functions for semiconductor devices.

Abstract: The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the transmitting device is capable of automatic compensation of cross-talk timing errors in the interface device, for a group of signals, by using information stored in a storage attached to that interface device. Preferably, the data stored in said storage comprises data on interconnections between said first and second plurality of terminals and data on crosstalk timing errors in said transmission lines relating to a specific data pattern, for each of said stored interconnection.

Abstract: A method for producing a probe unit for contacting an electronic circuit such as a wafer or a die having a predetermined pattern of contact pads deployed in a common plane. The method employes a base plate of made of a material capable of surface uplift when irradiated. On the surface of the base plate locations corresponding to said contact pads are determined. Further, the base plate is irradiated at the determined locations by means of a laser. This results in forming conical surface uplifts. The method further includes plating the conical surface uplifts with an electrically conductive material and providing means for electical connection between said plated conical surface uplifts and an external device.

Abstract: A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.

Abstract: A system for transformation of memory device addresses between different memory device topologies, each topology having its address space, providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach which allows mapping of memory device divided into an arbitrary number of tiles, each tile having different mapping scheme from a wide spectrum of mapping classes.

Abstract: The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips.

Abstract: Low swing communication system wherein the output driver's signal is used to adjust the driver's swing to the receiver's parameters, in particular, the hysteresis at the receiver. The receiver generates a signal indicative of parameters bearing information on the maximum and minimum levels, e.g. voltage, current or other levels, to cause a signal to be received as a logical one and as a logical zero. This parameter signal may be digital, but is preferably a differential analogue signal. The parameters influence the signal swing of the driver.

Abstract: A system, a method and a computer program product for defining transforms of cell addresses between different memory device topologies providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach offering a user friendly interface and simplification of the transformation procedure.

Abstract: The present invention relates to the reducing of timing uncertainties in high-performance digital circuitry. More specifically, the present invention relates to a timing control means and method for minimizing timing uncertainties due to skew and jitter. A means for the compensation of timing errors in multiple channel electronic devices comprising at least one register having a plurality of channels comprises: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's timing, the feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence and a set of delay means which uses the detected values of probability to generate a feedback signal.

Abstract: A system for reducing or obviating the requirement for a large amount of defect capture memory in memory test and analysis systems by compressing test results. The compression means system reduces or replaces the fault capture memory in the test system or workstation or both, a major cost in test system, while providing for subsequent regeneration of the test results, either without loss, or with the loss of certain features immaterial to the application.

Abstract: A fault tolerant semiconductor memory system has a main memory (1) having a first plurality of individually addressable storage locations. The system additionally has means for storing the address of ones of the storage locations which are defective, substitute memory comprising a second plurality of individually addressable storage locations mapped to corresponding ones of the defective storage locations, and control means comprising a plurality of comparators (20, 21, 23) for comparing a received address signal with a respective one of the addresses of the defective storage locations, each comparator being directly coupled to a corresponding one of the substitute storage locations, wherein read and write access can be re-routed from a defective storage location to the corresponding substitute storage locations.

Abstract: The present invention relates to an adaptive telephone interface for use in a telephone apparatus comprising a telephone terminal including signal amplifier means, and audio/input device. The telephone interface is disposable between the terminal and the audio/input device, and comprises a processor for generating a test signal and sending this to the terminal at a plurality of different amplitudes. The processor is further formed and arranged for monitoring signals returned from the terminal by means of sidetone coupling, so as to identify the test signal amplitude at which clipping of at least part of the test signal occurs, and consequentially adjusting the amplification by the interface of a signal received from the audio input device, before sending it on to the terminal so as to avoid substantially clipping thereof by the terminal signal amplifier means in use of the telephone apparatus.

Abstract: An electrostatographic single-pass multiple station multi-colour printer for forming an image onto a web. The printer has a plurality of toner image-printing electrostatographic stations. Each station has a drum onto the surface of which a toner image can be formed. An exposure station forms an electrostatic toner image line-wise on each drum surface. A corona device transfers the toner image onto the web, which is conveyed in succession past the stations in synchronism with the rotation of the drum surface. A register control device is provided for controlling the operation of each of the stations in timed relationship thereby to obtain correct registering of the distinct toner images on the web. The register control device includes an encoder driven by the displacement of the web to produce pulses indicative of web displacement, and delay system arranged to initiate the operation of subsequent stations after a predetermined web displacement, as measured by the encoder, has occurred.

Abstract: A process for reducing the test requirements of memory devices once they are packaged into modules by using a unique identification of a memory device based on the locations or types and locations of some of the defects in that memory device. The unique identification is used as an index to access a database containing more information on the types and locations of defects within that memory device. The information is then stored in a non-volatile memory on the module containing that memory device.