Abstract: A charge pump provides matched charging and discharging currents. One transistor is connected to an input of a charge pump core while two transistors are connected to the other input of the charge pump core, with each of the transistors mirroring a reference transistor through different mirroring pathways so that current through the transistor of the first input is equal to the sum of currents through the two transistors of the second input.

Abstract: A first charge module includes a first resistor and a first capacitor. A second charge module includes a second resistor and a second capacitor. A voltage comparison module includes a comparator connected to compare voltages present on the first and second capacitors. The comparator is connected to output a signal having a first state when the voltage on the first capacitor is less than the voltage on the second capacitor, and output a signal having a second state opposite of the first state when the voltage on the first capacitor is greater than the voltage on the second capacitor. A control module is configured to receive a PWM signal as an input signal and generate control signals based on the received PWM signal for controlling charging and discharging of the first and second capacitors. The output of the comparator is a decoded version of the PWM signal.

Abstract: A charge pump provides matched charging and discharging currents. One transistor is connected to an input of a charge pump core while two transistors are connected to the other input of the charge pump core, with each of the transistors mirroring a reference transistor through different mirroring pathways so that current through the transistor of the first input is equal to the sum of currents through the two transistors of the second input.

Abstract: An apparatus is configured to provide a voltage rising at the output with a programmable slew rate. The apparatus comprises a ramp-up control circuit module for supplying an increasing output voltage that is output to a load circuit. The ramp-up control circuit comprises an amplifier that receives the output of a plurality of selectable mirrored current sources that build up voltage across a capacitor for programming a selected linear slew rate for the increasing output voltage. The apparatus further comprises a glitch filter circuit for stabilizing the increasing output voltage so as to minimize glitches, including current and voltage stress, in the output voltage.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: A method of manufacturing an electronic circuit employing a flexible ramptime limit and an electronic circuit are disclosed. In one embodiment, the method includes: (1) physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, (2) performing a timing test on the physically synthesized electronic circuit employing the flexible ramptime limits and a processor and (3) determining if there is a violation of the flexible ramptime limits.

Abstract: Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.

Abstract: Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.

Abstract: A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit.

Abstract: One aspect provides a system for taking inter-clock correlation into account in on-chip timing derating. The system comprises a storage medium and an electronic design automation tool. The storage medium is configured to store data and clock path setup and hold early and late derate data. The electronic design automation tool is configured to employ at least some of said data and clock path setup and hold early and late derate data to calculate setup and hold slacks and total derate that take into account a correlation in delay variation between first and second clock paths as a function of depths thereof.

Abstract: An apparatus is configured to provide a voltage rising at the output with a programmable slew rate. The apparatus comprises a ramp-up control circuit module for supplying an increasing output voltage that is output to a load circuit. The ramp-up control circuit comprises an amplifier that receives the output of a plurality of selectable mirrored current sources that build up voltage across a capacitor for programming a selected linear slew rate for the increasing output voltage. The apparatus further comprises a glitch filter circuit for stabilizing the increasing output voltage so as to minimize glitches, including current and voltage stress, in the output voltage.

Abstract: A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.

Abstract: A timing error sampling generator, a method of performing timing tests and a library of cells are provided. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.

Abstract: A system for, and method of, reducing IC timing derating for a path in an integrated circuit design. In one embodiment, the system includes an electronic design automation tool configured to (1) extract circuit data regarding cells in the path and (2) calculate a timing derating for the path based at least in part on a determination as to whether the cells are simple cells.

Abstract: A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.

Abstract: A computer-executed method for designing dummy metal object locations in an integrated circuit design. The method comprises the steps of: a) receiving an integrated circuit design as input; b) finding areas of the integrated circuit design that do not meet a minimum metal density requirement; c) finding areas of the integrated circuit design having a critical timing path; d) blocking empty routing tracks that are adjacent to critical nets of the critical timing paths located in step (c), for prospective dummy metal object placement for the areas commonly located in both of steps (b) and (c); and e) placing a minimum number of dummy metal objects in empty tracks such that the minimum metal density requirement is met for the areas that were found in step (b), but were not blocked in step (d).

Abstract: An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: A computer-executed method for designing dummy metal object locations in an integrated circuit design. The method comprises the steps of: a) receiving an integrated circuit design as input; b) finding areas of the integrated circuit design that do not meet a minimum metal density requirement; c) finding areas of the integrated circuit design having a critical timing path; d) blocking empty routing tracks that are adjacent to critical nets of the critical timing paths located in step (c), for prospective dummy metal object placement for the areas commonly located in both of steps (b) and (c); and e) placing a minimum number of dummy metal objects in empty tracks such that the minimum metal density requirement is met for the areas that were found in step (b), but were not blocked in step (d).

Abstract: A timing error sampling generator, a path monitor, an IC, a method of performing timing tests and a library of cells are provided. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.