Abstract: A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.

Abstract: A method of accurately estimating horizontal and vertical wire densities in a datapath or hardmac. The method provides that the datapath or hardmac is divided into areas, and mathematical expectations are calculated for full and partial horizontal and vertical segments for each of the areas. The mathematical expectations are summed for both the horizontal and vertical segments, and this is done for each connection within the datapath or hardmac in order to estimate both horizontal and vertical wire densities. A congestion map can be created, and 100% detail routing is effectively guaranteed as a result of using the method. Preferably, a model with minimum bends is used in areas with low wire density, and models with more bends are used in areas with middle and high wire density.

Abstract: A method of noise analysis and correction of noise violations for an integrated circuit design includes steps of receiving as input a standard parasitic exchange file for an integrated circuit design and parsing the standard parasitic exchange file to generate a resistance graph. A representation of the resistance graph is generated to determine noise critical nets. A list is generated of only noise critical nets from the representation of the resistance graph. A net is selected from the list of only noise critical nets, and a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net is calculated. The value of total crosstalk noise in the selected net is generated as output for correcting a noise violation.

Abstract: A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing; (d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c); (e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and (f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

Abstract: A method and computer program product for estimating total path delay in an integrated circuit design includes steps of: (a) receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design; (b) calculating a sum of the stage delays; (c) calculating a worst case sum of the stage delay variations; (d) calculating a root-sum-square of the stage delay variations; (e) calculating a value of a weighting function; (f) calculating a weighted sum of the worst case sum of the stage delay variations and the root-sum-square of the stage delay variations from the weighting function; and (g) generating as output the weighted sum as a total path delay.

Abstract: A method of estimating crosstalk delay for an integrated circuit design flow includes steps of: (a) receiving an integrated circuit design; (b) selecting a list of blocks for which crosstalk delay is to be estimated from the integrated circuit design; (c) selecting one of a plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm for each block in the list of blocks; (d) performing the selected one of the plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm to estimate a delay for each block in the list of blocks; and (e) generating as output the estimated delay for each block in the list of blocks.

Abstract: A method of cell placement and clock tree synthesis includes steps of: (a) identifying critical paths in an integrated circuit design; (b) partitioning the integrated circuit design into a timing group for each of the critical paths; (c) assigning each flip-flop in a critical path to a timing group corresponding to the critical path; (d) performing a cell placement to minimize a function of propagation delay and maximum distance between flip-flops within each timing group; and (e) constructing a clock sub-net for each timing group.

Abstract: A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an area for placing module cells for each module in the plurality of modules wherein for each module that overlaps the internal I/O ring, an area of intersection between the area defined for placing the module cells and an area bounded by a side of the internal I/O ring for which the area of intersection is least is a global minimum for the plurality of modules; and (c) generating as output the floorplan for the integrated circuit architecture.

Abstract: A coaxial shield for a semiconductor chip includes: a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield; a first side shield wire formed in an intermediate metal layer of the semiconductor chip; a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length; a second side shield wire formed in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the len

Abstract: A coaxial shield for a semiconductor chip includes: a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield; a first side shield wire formed in an intermediate metal layer of the semiconductor chip; a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length; a second side shield wire formed in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the len

Abstract: A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing; (d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c); (e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and (f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

Abstract: A method of protecting a net of an integrated circuit against injected crosstalk delay includes receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure. The signal path structure is analyzed to calculate a skew correction and a net ramptime for the selected net. An injected crosstalk delay of the selected net is estimated from a net aggressor. A crosstalk protection scheme is selected for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

Abstract: A system, method and program product for designing integrated circuits. A design of an integrated circuit (IC) is analyzed to identify the longest path for each cell pair. The total path delay of each identified longest path is calculated. Net delays are calculated for each cell pair. A crosstalk overhead delay is calculated for each identified longest path using a stochastic model. The crosstalk overhead of each longest path is added to the calculated path delays. The circuit is redesigned to eliminate any path wherein the delay exceeds a maximum accepted delay. The stochastic model may be a tree-like structure derived from several completed integrated circuit designs, in particular from cell placement and wiring for each completed IC. The tree-like stochastic model corresponds crosstalk delays to technology wiring factors.

Abstract: A system, method and program product for designing integrated circuits. A design of an integrated circuit (IC) is analyzed to identify the longest path between each pair of registers. A crosstalk overhead is calculated for each identified longest path using a stochastic model. The crosstalk overhead of each longest path is added to selected path delays as an incremental port of register set up time. Any path wherein the sum of the path delay and crosstalk overhead exceeds a maximum accepted delay, i.e., where slack is less than or equal to zero is redesigned and the IC is then, placed and wired. The stochastic model may be a tree-like structure derived from several completed integrated circuit (IC) designs, in particular from cell placement and wiring for the completed IC. The tree-like stochastic model corresponds crosstalk delays to technology wire factors.

Abstract: An improved method of using the Elmore Model to estimate the delay which is associated with the a clock buffer output. The improved method provides that the clock buffer output resistor is taken into account when the Elmore Model is used to calculate the delay. Also provided is a method of using the Elmore Model to estimate wire delay, where the method includes steps of calculating an approximate delay based on a distributed RC model, and using a capacitance value corresponding to the approximate delay in the Elmore Model to estimate the wire delay.

Abstract: A method of noise analysis and correction of noise violations for an integrated circuit design includes steps of (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a noise violation.

Abstract: A method of cell placement and clock tree synthesis includes steps of: (a) identifying critical paths in an integrated circuit design; (b) partitioning the integrated circuit design into a timing group for each of the critical paths; (c) assigning each flip-flop in a critical path to a timing group corresponding to the critical path; (d) performing a cell placement to minimize a function of propagation delay and maximum distance between flip-flops within each timing group; and (e) constructing a clock sub-net for each timing group.

Abstract: A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.

Abstract: A global interconnect distribution system is disclosed. The global interconnect distribution system includes a global interconnect cell capable of producing at least two substantially identical output signals, and a global interconnect coupled to the cell for carrying one of the output signals. At least one wire is also coupled to the cell that is routed adjacent to the global interconnect for carrying the other output signal to provide active shielding for the global interconnect, thereby increasing signal integrity and signal transmission of the global interconnect.

Abstract: A method of estimating crosstalk delay for an integrated circuit design flow includes steps of: (a) receiving an integrated circuit design; (b) selecting a list of blocks for which crosstalk delay is to be estimated from the integrated circuit design; (c) selecting one of a plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm for each block in the list of blocks; (d) performing the selected one of the plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm to estimate a delay for each block in the list of blocks; and (e) generating as output the estimated delay for each block in the list of blocks.