Abstract: Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point.

Abstract: A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.

Abstract: A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control.

Abstract: A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal.

Abstract: A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control.

Abstract: A system in one embodiment includes a voltage controlled oscillator; at least two varactors coupled to a tank node, each of the varactors being of a different physical size, the tank node being coupled to the voltage controlled oscillator; and switches for selectively turning the varactors on and off, wherein switching a first of the varactors from off to on and a second of the varactors from on to off creates a capacitance step of less than about 10 fF thereby tuning the voltage controlled oscillator from a first state to a second state.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A technique is disclosed for processing a binary coded signal to generate a thermometer coded signal. Such technique includes the following steps. A binary coded input signal is obtained. A binary arithmetic operation is performed on a least significant bit (LSB) portion of the binary coded input signal. At least one signal representative of an occurrence of one of an overflow condition and an underflow condition is generated, in response to the binary arithmetic operation performed on the LSB portion. A thermometer coded signal is shifted in response to the signal representative of the occurrence of one of the overflow condition and the underflow condition, wherein shifting of the thermometer coded signal represents one of incrementing and decrementing a most significant bit (MSB) portion of the binary coded input signal. The thermometer coded signal is outputted.

Abstract: A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith.

Abstract: Multiple-input CML gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.

Abstract: Multiple-input CML gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.

Abstract: A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith.