Abstract: Embodiments of the present disclosure relate to an radio frequency (RF) power amplifier (PA) module having a saturation corrected integration loop, which includes saturation detection and correction circuitry, an integrator, PA circuitry, and detector circuitry. An integrator output signal from the integrator is prevented from being driven toward a power supply rail in the presence of saturation of the PA circuitry by saturation correction of an input ramp signal. The saturation detection and correction circuitry receives and saturation corrects the input ramp signal to provide a saturation corrected input ramp signal to the integrator based on detecting saturation of the PA circuitry. Saturation of the PA circuitry is detected based on a difference between a desired PA output voltage, as indicated by the input ramp signal, and a detected PA output voltage, as indicated by a detector output signal from the detector circuitry.

Abstract: Disclosed is a method in which slaves are cascaded on a bus, and cascading slave-to-slave communication is used to prioritize (or sequence) the software slave ID programming, enabling users to uniquely identify identical components in a circuit. In one embodiment, the first slave in the cascade stalls the programming of other slaves until the first slave's programming is complete. Once completed, the first slave then enables programming of the second slave, and so on. This embodiment allows multiple placements of identical slaves on the bus, and provides a method to uniquely identify and control each slave by using cascading software slave ID programming. In another embodiment, a structure with a similar effect may be created by lack of enablement (instead of disablement), wherein initially only the first slave is enabled, and subsequent slaves are not initially enabled. Additionally, the present disclosure is compatible with the MIPI RFFE standard interface.

Abstract: RF amplifier control circuits for transmitters in mobile communication devices, combinations thereof and methods therefor. The control circuits include generally proportional and integral control circuits having an output coupled to a control input of an amplifier. An initial control signal is applied to the amplifier before a vector modulator output coupled an input thereof is at full output power. The vector modulator output is ramped to full output after applying the initial control signal. Thereafter, the initial control signal applied to the amplifier during ramping is corrected by integrating an output of the amplifier relative to a second reference signal with an integral control circuit coupled to the control input of the amplifier, the second reference signal is proportional to the ramping vector modulator output.

Abstract: RF amplifier control circuits for transmitters in mobile communication devices, combinations thereof and methods therefor. The control circuits include generally proportional and integral control circuits having an output coupled to a control input of an amplifier. An initial control signal is applied to the amplifier before a vector modulator output coupled an input thereof is at full output power. The vector modulator output is ramped to full output after applying the initial control signal. Thereafter, the initial control signal applied to the amplifier during ramping is corrected by integrating an output of the amplifier relative to a second reference signal with an integral control circuit coupled to the control input of the amplifier, the second reference signal is proportional to the ramping vector modulator output.

Abstract: A radio communication device provides extended burst tone detection for a demodulated I and Q input signal. The device includes a first burst detector coupled with the input signal and provides a first detection signal when a FCB tone is detected. A frequency shifter is coupled with the input signal and frequency translates the input signal by a predetermined amount. A second burst detector is coupled with the translated input signal and provides a second detection signal when a FCB tone is detected. A combiner is coupled with the first and second detection signals and indicates FCB tone detection when either of the first and second detection signals indicate FCB tone detection.

Abstract: A PLL (225) includes a phase detector (202) and a charge pump (210 or 212). The phase detector (202) includes a first D-type flip flop (302), a second D-type flip flop (304) and an AND gate forming a reset circuit (306). The charge pump (210 or 212) includes an up current source (308) and a down current source (310). The up current source (308) provides a constant current. The down current source (310) varies responsive to an output signal (207) generated by the second D-type flip flop (304). The constant current provided by the up current source (308) is made to be less than one half the current provided by the down current source (310) to bias the charge pump (210 or 212) in a negative direction to minimize false locks between the phase of a divided reference frequency signal (206) and the phase of a divided voltage controlled oscillator frequency signal (209).

Abstract: By employing AFC range extension, a high frequency communication device (100) can use a low cost, low accuracy crystal (119) in its reference oscillator (118). AFC range extension involves varying receive bandwidth of the communication device (100) to facilitate AFC or automatic frequency control. In particular, the receive bandwidth is set to a first, wide setting for AFC acquisition purposes (208). Frequency error associated with a received AFC signal is determined (212) and receive reception is adjusted (218) to reduce frequency error in the communication device (100). Once the frequency error is below a predetermined threshold (214), the receive bandwidth is set to a second setting different from the first setting for normal reception (220).

Abstract: A wireless communication device (202), such as a cellular telephone, has a power amplifier (218) and a power amplifier control (222). The power amplifier (218) is selectively controllable to amplify, to different output power levels, a signal for transmission. In a high power mode requiring amplification of the signal to a high output power level, the power amplifier control (222) controls the power amplifier to amplify the signal according to a predetermined amplitude waveform (106). In a low power mode requiring amplification of the signal to a low output power level, the power amplifier control controls the power amplifier to amplify the signal according to a delayed one of the predetermined amplitude waveform (300).

Abstract: A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).

Abstract: The preferred embodiment of the present invention encompasses an automatic frequency control system implemented in a radiotelephone (101). The radiotelephone (101) includes a frequency synthesizer. The frequency synthesizer uses a division ratio varied with time by a multi accumulator fractional N synthesizer (140) such that the effective division ratio may be varied by non-integer steps. The division ratio is programmed to realize the desired channel frequency, the desired modulation waveform, and any automatic frequency correction offset. An accurate clock is provided to the control logic (104) and the user interface (105) sections of the radiotelephone (101) using a second multiple accumulator fractional N division system (139). This second fractional N division system (139) is programmed based on the automatic frequency control programming of the first fractional N synthesizer (140).

Abstract: A TC controlled RF signal detecting circuitry (211) used in the output power control circuit of a TDMA RF signal power amplifier includes positive coefficient current source (303) producing current I+ having a positive TC, negative coefficient current source (305) producing current I- having a negative TC, and current mirror (301) for summing currents I+ and I- to produce substantially identical compensated mirror currents Im1 and Im2. Anti-clamping current mirror (309) mirrors current Im2 to produce compensated currents Ia1 and Ia2, which are applied to and bias a Schottky diode coupled in series to a resistor network in each leg of diode detector (311). Each leg of diode detector (311) has a positive TC, which is substantially offset by the negative TC of compensated currents Ia1 and Ia2.

Abstract: Transmitting signals containing amplitude modulated (AM) and phase modulation (PM) components requires a transmitter having AM and PM control loops. The PM control loop provides phase modulation, frequency translation and phase predistortion for the transmitter. The phase predistortion/correction is accomplished by using an oscillator, thus, the amount of PA phase correction is essentially unlimited. Additionally, the PM control loop is nested about a power amplifier (PA), allowing the PM control loop to correct for any distortion introduced by the PA.

Abstract: A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.

Abstract: A power amplifier controller for detecting saturation of the power amplifier (203) and corrects the automatic output control voltage (231) to avoid any further saturation. A detector (211) detects the power of the radio frequency (RF) output signal (211) and generates a signal (229) correlated to the detected power. Comparator (217) compares changes in that signal (229) to changes in the voltage of the AOC signal (231). The comparator (217) generates a signal (233) correlated to saturation of the power amplifier (203) for a DSP (223). The DSP (223) checks the status of this signal (233). Upon detecting saturation, an algorithm contained within the DSP methodically reduces the voltage of the AOC signal (231) until there is a change in the power of the RF output signal (211).

Abstract: A fractional-N type frequency synthesizer (700) for use in a radiotelephone (901). The synthesizer (700) utilizes multiple latched accumulators (401, 403, 405, 407), within an accumulator network, to perform multiple integrals of an input signal (439). The outputs of the accumulators are combined in series to form a data output signal (453). The data output signal (453) is input to a divider network (703) and used as a variable divisor of the frequency input from a variable oscillator (701) into the divider network (703).

Abstract: The present disclosure includes a discussion of a power amplifier controller which powers up a power amplifier (203) without a substantial burst of frequency noise. The controller has a RF output power detector (211) which generates a signal (229) correllated to the power level of the power amplifier (203). This signal (229) is compared (215) to a reference signal (213) to determine if the power amplifier (203) is active. The signal (227) generated by this comparator (215) is used to determine the voltage level of the Automatic Output Control (AOC) signal (231).

Abstract: A voltage controlled oscillator and buffer amplifier circuit (211) is disclosed. The circuit is in a stacked configuration, whereby, the current from the power supply (361) is used by the buffer amplifier circuit and reused by the VCO circuit. The VCO circuit includes two transistors (333, 325). The transistors are set-up in a mirrored configuration, so that one of the transistors (325) controls the bias current in the other transistor (333). Both of the transistors are integrated into a semiconductor circuit die (365), thus, matching the thermal characteristics of the transistors (333, 325) and improving control of the bias current. The die (365) is bonded to a ceramic substrate (601). The substrate (601) has connectivity paths for connecting components in the circuit die to components external to the circuit die. Some of the connectivity paths are made of a material and length to form passive circuit elements.

Abstract: A fractional-N synthesizer realizes automatic frequency control by adding (509) a digital representation of a determined frequency offset to a digital representation of applied modulation to create the modulus control of a programmable frequency divider (203).

Abstract: A latched accumulator fractional-N synthesizer having reduced residual error for use in digital radio transcievers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615,617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).

Abstract: A multiple latched accumulator fractional-N synthesizer for use in digital radio transceivers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The carry outputs of each accumulator are coupled through delays (645, 647, 649, 631, 633) equal to one less delay than the number of accumulators and added (635) such that all higher order accumulator carry outputs add to a net summation of zero so as to not upset the desired fractional setting of the first accumulator.