Abstract: In a PLL synthesizer, the tolerance to gain and component variations is greatly reduced when the gain of the loop in increased above that which the loop was initially designed for and if the third order loop symmetric ratio is reduced to a value within the range of 2.0 to 2.5. Higher order loops based on the third order symmetric ratio range have correspondingly lower transmission pole frequency to open unity gain frequency ratios.

Abstract: A frequency synthesizer having a frequency divider and a frequency multiplier in the feedback loop is disclosed. The minimum frequency separation between two adjacent synthesized channels is equal to the reference frequency divided by the multiplication ratio of the multiplier. The division ratio of the frequency divider, which can be analyzed as the sum of an integer and a fractional portion, is varied with time by a digital sequence, resulting in a minimum frequency increment equal to a fraction of the reference frequency. The multiplier acts to reduce the nonlinearities of the frequency synthesizer when the fractional portion of the division ratio causes a large variation in the instantaneous division ratio by reducing the effective division ratio of the loop.

Abstract: A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.

Abstract: An RF signal input circuit for a UHF tuner of a television receiver comprises a series-tuned circuit including a varactor diode and an inductance element connected in series, in the order named, between signal ground and a gate electrode of a field-effect transistor RF amplifier. The series-tuned circuit has a relatively uniform bandwidth throughout the UHF range. A capacitor connected in shunt with the gate electrode completes a "split-capacitor" configuration in which the varactor diode and the shunt capacitor form a variable impedance transformation network for making the relationship between the effective impedances of the series-tuned circuit and FET amplifier relatively uniform throughout the UHF range. The order of the varactor diode and inductance element allows a low cost adjustable capacitor comprising a grounded shield wall as one plate and a movable tab as a second plate to be connected directly across the varactor diode.

Abstract: A continuously adaptive phase locked loop synthesizer is disclosed in which error correction pulses from a phase detector are separated into narrow pulse width and wide pulse width pulses. The wide pulse width pulses are coupled to the loop filter to enable a rapid charge of the loop filter to provide a VCO control voltage on a control line connected to the output of the loop filter. The narrow pulse width pulses are filtered by a narrow bandwidth filter before being applied to the loop filter thus enabling a slow charge of the loop filter. The narrow bandwidth filter is decoupled from the control line but referenced to the control line voltage.

Abstract: A unitary tuning structure of a UHF tuner includes an inductance loop, an inductance adjustment element attached to a top portion of the inductance loop so as to be foldable with respect to the inductance loop about an axis parallel to the printed circuit board to which the inductance loop is attached and a capacitance adjustment tab attached to a side portion of the inductance loop so as to be foldable with respect to the inductance loop about an axis perpendicular to the printed circuit board. In another form of the unitary tuning structure, a second inductance loop can be attached within the first loop.