Patents by Inventor Alexis Gauthier

Alexis Gauthier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057521
    Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • Publication number: 20210057520
    Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • Publication number: 20200411381
    Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Gregory AVENIER, Alexis GAUTHIER, Pascal CHEVALIER
  • Publication number: 20200411382
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
  • Patent number: 10622460
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Guillaume C. Ribes
  • Publication number: 20200111889
    Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER
  • Publication number: 20200111890
    Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER
  • Publication number: 20200013856
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER
  • Patent number: 10468508
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 5, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
  • Patent number: 10453919
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Alexis Gauthier
  • Publication number: 20190267473
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Guillaume C. RIBES
  • Publication number: 20190259838
    Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Julien BORREL
  • Patent number: 10332982
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 25, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Guillaume C. Ribes
  • Publication number: 20190148531
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • Publication number: 20190140072
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Alexis Gauthier
  • Patent number: 10224423
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: March 5, 2019
    Assignee: STMircoelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
  • Patent number: 10186605
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Fabien Deprat, Yves Campidelli
  • Publication number: 20180277659
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Application
    Filed: September 18, 2017
    Publication date: September 27, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Guillaume C. Ribes