Patents by Inventor Alfio Guarnera

Alfio Guarnera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11495508
    Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: November 8, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Simone Rascuna′, Claudio Chibbaro, Alfio Guarnera, Mario Giuseppe Saggio, Francesco Lizio
  • Publication number: 20220344467
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Application
    Filed: May 10, 2022
    Publication date: October 27, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20220262913
    Abstract: A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 18, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Alfio GUARNERA, Cateno Marco CAMALLERI
  • Publication number: 20220246729
    Abstract: A vertical conduction MOSFET device includes a body of silicon carbide, which has a first type of conductivity and a face. A superficial body region of a second type of conductivity has a first doping level and extends into the body to a first depth , and has a first width. A source region of the first type of conductivity extends into the superficial body region to a second depth, and has a second width. The second depth is smaller than the first depth and the second width is smaller than the first width. A deep body region of the second type of conductivity has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, and the second doping level is higher than the first doping level.
    Type: Application
    Filed: December 29, 2021
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI, Alessia Maria FRAZZETTO, Alfio GUARNERA, Cateno Marco CAMALLERI, Antonio Giuseppe GRIMALDI
  • Publication number: 20220246723
    Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.
    Type: Application
    Filed: January 19, 2022
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Alessia Maria FRAZZETTO, Edoardo ZANETTI, Alfio GUARNERA
  • Patent number: 11329131
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti, Alfio Guarnera
  • Publication number: 20210399089
    Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 23, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Angelo MAGRI', Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20210249268
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo ZANETTI, Simone RASCUNA', Mario Giuseppe SAGGIO, Alfio GUARNERA, Leonardo FRAGAPANE, Cristina TRINGALI
  • Patent number: 11018008
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 25, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo Zanetti, Simone Rascuná, Mario Giuseppe Saggio, Alfio Guarnera, Leonardo Fragapane, Cristina Tringali
  • Publication number: 20210151563
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 20, 2021
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20210104445
    Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 8, 2021
    Inventors: Simone RASCUNA', Claudio CHIBBARO, Alfio GUARNERA, Mario Giuseppe SAGGIO, Francesco LIZIO
  • Publication number: 20190172715
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 6, 2019
    Inventors: Edoardo ZANETTI, Simone RASCUNÁ, Mario Giuseppe SAGGIO, Alfio GUARNERA, Leonardo FRAGAPANE, Cristina TRINGALI
  • Patent number: 8901652
    Abstract: An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: December 2, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera, Simone Rascuna′
  • Patent number: 8866223
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 21, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 8853779
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 8828809
    Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera
  • Publication number: 20130244397
    Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.
    Type: Application
    Filed: May 3, 2013
    Publication date: September 19, 2013
    Applicant: STMicroelectronics S.r.I.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera
  • Patent number: 8455318
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 8455956
    Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera
  • Publication number: 20120187479
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 26, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina