Abstract: A method of performing proximity correction of a mask layout is used during the generation of a masking structure for performing a processing step. The masking structure includes at least one opening that is delimited by a sidewall and that exposes an area that is to be processed. The method includes the steps of a) determining a value representing a flux of particles to a target portion, wherein the target portion is at least one of the group of a portion of the sidewall and a portion of the uncovered area and wherein the particles are generated during the processing of the area; and b) determining a corrected mask layout dependent on the value determined in step a).

Abstract: One possible embodiment is a method for manufacturing a structure on a substrate which can be used in the manufacturing of a semiconductor device, including the steps of: forming a first structure on the substrate having at least one sidewall, forming at least one layer as a second structure selectively on the at least one sidewall of the first structure by an epitaxial technique, electroplating, selective silicon dioxide deposition, selective low pressure CVD or an atomic layer deposition technique. Furthermore semiconductor devices, uses of equipment and structures are covered.

Abstract: A method and system determines deformations in a substrate in the manufacturing of semiconductor devices. At least one property of vertical deformations of the substrate is measured at a plurality of locations on the substrate. Afterward, an automatic computation of horizontal deformations is determined based on the measured properties of vertical deformations with a model for the deformation behavior of the substrate.

Abstract: The present invention relates to a deposition of a dielectric layer. On a substrate having a structured area a crystallization seed layer for a dielectric layer is deposited via an atomic layer deposition technique employing a first and a second precursor on the structured area of the substrate. The first pre-cursor is a compound having the constitutional formula M1(R1Cp)x(R2)4-x, wherein M1 is one of hafnium and zirconium, Cp is cyclopentadienyl, R1 is independently selected of methyl, ethyl and alkyl, R2 is independently selected of hydrogen, methyl, ethyl, alkyl and alkoxyl, and x is one or two. The dielectric layer is deposited on the crystallization seed layer via an atomic layer deposition technique employing a third and a forth precursor wherein the third pre-cursor being a compound having the constitutional formula M2 R3 R4 R5 R6, wherein M2 is one of hafnium or zirconium and R3, R4, R5, and R6 are independently selected of alkyl amines.

Abstract: In one aspect, the invention provides a fabrication method. Before the fabrication of the structure, a mask layer, for example a hard mask, is applied to a layer. The mask layer has at least two layers composed of materials that can be etched selectively with respect to one another. In a first etching process, the structure is introduced into the layer. Subsequently, the first etching process is interrupted at a point in time in order to etch away a topmost layer of the hard mask selectively with respect to the underlying layer by means of a second etching process and, subsequently, the first etching process is continued for fabricating the structure with the new topmost layer.

Abstract: An annular microstructure element, in particular an annularly arranged monolayer or multilayer thin film, is formed over a substrate (S), e.g., for use in a magnetoresistive memory. To that end, a masking layer is applied over the substrate. An opening (C) is etched into the masking layer, so that a partial region of the surface is uncovered. The etching operation is performed in such a way that the opening (C) is formed with an overhang (B). The overhang at least partially shades the uncovered surface from an incident particle beam (TS). A particle beam (TS) is directed at the substrate (S) at an oblique angle (?) of incidence. In this case, the substrate (S) is rotated relative to the directed particle beam (TS). From the particle beam, material is thereby deposited annularly on the uncovered surface for the purpose of forming a hole-like microstructure element (R).

Abstract: A method and apparatus for providing a gaseous precursor for a coating process. A starting material having a pulverulent precursor material is heated in order to cause a vaporization of the pulverulent precursor material, whereby a gaseous precursor is produced. A carrier gas is flowed past the starting material at a distance minimizing or preventing a convective gas flow, while transporting the gaseous precursor to a processing region containing a wafer to be coated.

Abstract: The atomic layer deposition process according to the invention provides the following steps for the production of homogeneous layers on a substrate. The substrate is introduced into a reaction chamber. A first precursor is introduced into the reaction chamber, which first precursor reacts on the surface of the substrate to form an intermediate product. A second precursor is introduced into the reaction chamber, which second precursor has a low sticking coefficient and reacts with part of the intermediate product to form a first product. A third precursor is introduced into the reaction chamber, which third precursor has a high sticking coefficient and reacts with the remaining part of the intermediate product to form a second product. The second precursor and its first product reduce the effective sticking coefficient of the third precursor by partially covering the surface.

Abstract: A PVD method and a PVD apparatus use a rotating magnetic field in order to increase the yield. The magnetic field is provided such that it essentially vanishes, at least in a time average, outside a rotation axis of the magnetic field in sectors of the target region of the PVD apparatus. In this manner the PVD method and the PVD apparatus achieve a uniform coating.

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract: An annular microstructure element, in particular an annularly arranged monolayer or multilayer thin film, is formed over a substrate (S), e.g., for use in a magnetoresistive memory. To that end, a masking layer is applied over the substrate. An opening (C) is etched into the masking layer, so that a partial region of the surface is uncovered. The etching operation is performed in such a way that the opening (C) is formed with an overhang (B). The overhang at least partially shades the uncovered surface from an incident particle beam (TS). A particle beam (TS) is directed at the substrate (S) at an oblique angle (?) of incidence. In this case, the substrate (S) is rotated relative to the directed particle beam (TS). From the particle beam, material is thereby deposited annularly on the uncovered surface for the purpose of forming a hole-like microstructure element (R).

Abstract: An inner contour of the compensation frame (2) is configured in polygonal fashion in order to receive the substrate (1). With the substrate (1) having been received, the compensation frame (2) encloses the substrate (1) at the outer edge thereof. A partial region (3a) of an upper main area (3) of the compensation frame (2) runs at a given height (h) above the plane of an upper main area (1a) of the substrate (1) when the latter has been received into the compensation frame (2). Moreover, a further partial region (3b) of the upper main area (3) of the compensation frame runs essentially at the same height as the plane of the upper main area (3) of the substrate (1) when the latter has been received into the compensation frame (2).

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract: A reaction chamber for processing a substrate wafer is described. The reaction chamber has a wafer holder for receiving the substrate wafer, a convection plate, which is disposed above the wafer holder, for suppressing convective movements over the substrate wafer, and a gas distributor plate which is disposed on a side face of the reaction chamber, for distributing process or purge gases that flow in. A flow plate is disposed on the gas distributor plate and extends substantially in a plane that is perpendicular to the gas distributor plate. This allows rapid and efficient purging of the reaction chamber.

Abstract: A PVD method and a PVD apparatus use a rotating magnetic field in order to increase the yield. The magnetic field is provided such that it essentially vanishes, at least in a time average, outside a rotation axis of the magnetic field in sectors of the target region of the PVD apparatus. In this manner the PVD method and the PVD apparatus achieve a uniform coating.

Abstract: A chemical mechanical polishing process rotates a wafer having an alignment mark at a wafer rotation rate and a polishing surface at an off-matched rotation rate. The wafer rotation rate and the off-matched rotation rate are not equal. The wafer rotating at the wafer rotation rate and the polishing surface rotating at the off-matched rotation rate touch to polish a plurality of points on the wafer. The rotation of the wafer rotating at the wafer rotation rate is adjusted with respect to the polishing surface rotating at the off-matched rotation rate to achieve an approximately zero averaged rotation rate velocity for each of the points on the wafer with respect to the polishing surface polishing the wafer upon a completion of the total polishing time.

Abstract: A method for determining relevant deposition parameters in i-PVD processes, includes, first calculating the reaction rates for desired reagents of the gas plasma and of a metal and/or metal compound to be deposited, then simulating the edge coverage of a predetermined structure with the deposited metal based upon the calculated reaction rates with systematic variation of the relevant deposition parameters, and compiling variant tables therefrom. By comparing an experimental verification of the simulated edge coverage by imaging the edge coverage of the metal layer deposited over the determined structure, e.g., using a TEM cross-section, with the simulated deposition parameters for the edge coverages that have been recorded in the variant table, it is possible to read the deposition parameters that are of relevance to the process from the variant table.

Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

Abstract: A chemical mechanical polishing process rotates a wafer having an alignment mark at a wafer rotation rate and a polishing surface at an off-matched rotation rate. The wafer rotation rate and the off-matched rotation rate are not equal. The wafer rotating at the wafer rotation rate and the polishing surface rotating at the off-matched rotation rate touch to polish a plurality of points on the wafer. The rotation of the wafer rotating at the wafer rotation rate is adjusted with respect to the polishing surface rotating at the off-matched rotation rate to achieve an approximately zero averaged rotation rate velocity for each of the points on the wafer with respect to the polishing surface polishing the wafer upon a completion of the total polishing time.

Abstract: The present invention relates to a system for executing a plasma-based sputtering method, such as for example a PVD (Physical Vapor Deposition) method. In a process chamber (1), a plasma (2) is produced in order to accelerate ionized particles, carried away from a sputter target (21), through the plasma (2) towards a substrate (3), using an electrical field. In the process chamber (1), between the plasma (2) and the substrate (3) a magnetic field component (6) is produced by that is situated parallel to a substrate surface (5). Through the magnetic field component (6), the angular distribution of the ionized particles is deflected from its flight path perpendicular to the substrate surface, so that impact angles are produced that have a greater angular scattering.