Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: The preferred embodiments described below provide a method and memory device for improving the precision of a temperature-sensor circuit. In one preferred embodiment, first and second temperature-dependent reference voltages are generated and compared, and an operating condition of the memory array is controlled based on the result of the comparison. Instead of using a temperature-dependent reference voltage, a temperature-dependent reference current can be used. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: The preferred embodiments described below provide a method and memory device for improving the precision of a temperature-sensor circuit. In one preferred embodiment, first and second temperature-dependent reference voltages are generated and compared, and an operating condition of the memory array is controlled based on the result of the comparison. Instead of using a temperature-dependent reference voltage, a temperature-dependent reference current can be used. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

Abstract: A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.

Abstract: An apparatus and method is disclosed for minimizing in band distortion in the transmit path of an XDSL modem. The transmit path of an XDSL modem introduces various non-linearities into transmissions in both the frequency and time domains. The current invention provides a means for both determining and correcting for distortion in the time domain. In an embodiment of the invention the apparatus may include a calibrator which may be implemented using the existing analog-to-digital (ADC) conversion and demodulation capabilities on the receive path of the modem or alternately, a dedicated module. During a calibration phase a training signal is injected digitally into the digital-to-analog converter of the transmit path. The analog portion of the transmit path is coupled to a calibrator which measures the corresponding analog response. The correlation between input and response is stored in an analog model.

Abstract: A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

Abstract: A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

Abstract: A flash memory having redundancy content addressable memory (CAM) circuitry is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array of memory cells, a redundant array of memory cells, and the redundancy CAM circuitry. The redundancy CAM circuitry includes a plurality of dual-ported CAM stages. Each CAM stage includes a CAM cell, a write data bus coupled to the CAM cell, and a read data bus coupled to the CAM cell. The CAM cell stores information regarding a location of an inoperative memory cell in the primary array. The inoperative memory cell requires a substitution with a second memory cell in the redundant array. The write data bus produces the information from the CAM cell responsively to a write select signal. The write select signal is indicative of a write operation to be performed at memory cell locations in the primary array.

Abstract: A flash memory having redundancy content addressable memory (CAM) circuitry is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array of memory cells, a redundant array of memory cells, and the redundancy CAM circuitry. The redundancy CAM circuitry includes a plurality of dual-ported CAM stages. Each CAM stage includes a CAM cell, a write data bus coupled to the CAM cell, and a read data bus coupled to the CAM cell. The CAM cell stores information regarding a location of an inoperative memory cell in the primary array. The inoperative memory cell requires a substitution with a second memory cell in the redundant array. The write data bus produces the information from the CAM cell responsively to a write select signal. The write select signal is indicative of a write operation to be performed at memory cell locations in the primary array.

Abstract: A memory device is split into two or more memory banks. Each bank includes a number of sectors. Each Sector includes memory cells. While one bank is busy with program operation, the other bank can be simultaneously engaged in program-verify operation during the same cycle.