Patents by Inventor Ali Al-Shamma
Ali Al-Shamma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210193230Abstract: A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.Type: ApplicationFiled: December 23, 2019Publication date: June 24, 2021Applicant: SanDisk Technologies LLCInventors: Yingchang Chen, Seungpil Lee, Ali Al-Shamma
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Patent number: 11031059Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.Type: GrantFiled: February 21, 2019Date of Patent: June 8, 2021Assignee: Sandisk Technologies LLCInventors: Christopher J. Petti, Tz-Yi Liu, Ali Al-Shamma, Yoocharn Jeon
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Patent number: 11024392Abstract: A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.Type: GrantFiled: December 23, 2019Date of Patent: June 1, 2021Assignee: SanDisk Technologies LLCInventors: Yingchang Chen, Seungpil Lee, Ali Al-Shamma
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Publication number: 20200401534Abstract: A memory device includes a memory module that encrypts and decrypts data with a key. To encrypt, the memory module performs a first modified XOR operation in which a ciphertext has a same logical value as a corresponding key when the data has a low logical value and the ciphertext has an inverse of the logical value of the corresponding key when the data is at a high logical value. To decrypt, the memory module performs a second modified XOR operation in which the logical value of the ciphertext forms the logical value of the data when the corresponding key is at the low logical value and the inverse of the logical value of the ciphertext forms the logical value of the corresponding data when the corresponding key is at the high logical value.Type: ApplicationFiled: June 24, 2019Publication date: December 24, 2020Applicant: SanDisk Technologies LLCInventors: Federico Nardi, Ali Al-Shamma
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Patent number: 10832770Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a single pulse memory operation. An electrical source is configured to generate an electrical pulse. A selector for a memory cell is configured to conduct an electrical pulse from an electrical source to a memory cell in response to the electrical pulse exceeding a threshold. A control circuit is configured to maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.Type: GrantFiled: March 13, 2019Date of Patent: November 10, 2020Assignee: SanDisk Technologies LLCInventors: Ali Al-Shamma, Yadhu Vamshi Vancha, Jeffrey Lee
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Patent number: 10803912Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.Type: GrantFiled: January 18, 2019Date of Patent: October 13, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Yadhu Vamshi Vancha, Ali Al-Shamma, Yingchang Chen, Jeffrey Lee, Tz-Yi Liu
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Publication number: 20200294584Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a single pulse memory operation. An electrical source is configured to generate an electrical pulse. A selector for a memory cell is configured to conduct an electrical pulse from an electrical source to a memory cell in response to the electrical pulse exceeding a threshold. A control circuit is configured to maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.Type: ApplicationFiled: March 13, 2019Publication date: September 17, 2020Applicant: SanDisk Technologies LLCInventors: ALI AL-SHAMMA, YADHU VAMSHI VANCHA, JEFFREY LEE
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Publication number: 20200273512Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.Type: ApplicationFiled: February 21, 2019Publication date: August 27, 2020Inventors: Christopher J. Petti, Tz-Yi Liu, Ali Al-Shamma, Yoocharn Jeon
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Patent number: 10734048Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.Type: GrantFiled: June 5, 2018Date of Patent: August 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Yadhu Vamshi Vancha, James Hart, Jeffrey Koon Yee Lee, Tz-Yi Liu, Ali Al-Shamma, Yingchang Chen
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Publication number: 20200234743Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.Type: ApplicationFiled: January 18, 2019Publication date: July 23, 2020Inventors: Yadhu Vamshi Vancha, Ali Al-Shamma, Yingchang Chen, Jeffrey Lee, Tz-Yi Liu
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Patent number: 10692570Abstract: Various examples for accelerating multiplication operations are presented, which can be employed in neural network operations, among other applications. In one example, a circuit comprises a non-volatile memory cell, and an input circuit coupled to a gate terminal of the non-volatile memory cell. The input circuit is configured to ramp a control voltage applied to the gate terminal at a ramp rate representing a multiplicand value. An output circuit coupled to an output terminal of the non-volatile memory cell and is configured to generate an output pulse based on the control voltage satisfying a threshold voltage of the non-volatile memory cell, where the output pulse has a duration comprising the multiplicand value multiplied by a multiplier value represented by the threshold voltage.Type: GrantFiled: November 19, 2018Date of Patent: June 23, 2020Assignee: SANDISK TECHNOLOGIES LLCInventor: Ali Al-Shamma
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Publication number: 20200020393Abstract: Various examples for accelerating multiplication operations are presented, which can be employed in neural network operations, among other applications. In one example, a circuit comprises a non-volatile memory cell, and an input circuit coupled to a gate terminal of the non-volatile memory cell. The input circuit is configured to ramp a control voltage applied to the gate terminal at a ramp rate representing a multiplicand value. An output circuit coupled to an output terminal of the non-volatile memory cell and is configured to generate an output pulse based on the control voltage satisfying a threshold voltage of the non-volatile memory cell, where the output pulse has a duration comprising the multiplicand value multiplied by a multiplier value represented by the threshold voltage.Type: ApplicationFiled: November 19, 2018Publication date: January 16, 2020Inventor: Ali Al-Shamma
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Publication number: 20190371380Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Inventors: Yadhu Vamshi Vancha, James Hart, Jeffrey Koon Yee Lee, Tz-Yi Liu, Ali Al-Shamma, Yingchang Chen
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Patent number: 10170162Abstract: A calibration circuit coupled to a sense amplifier circuit may be configured to determine a response time of the sense amplifier circuit relative to a pulse sequence. Based on the determined response time, the calibration circuit may be configured to set a level of a biasing current to a desired level in order to control the response time of the sense amplifier circuit.Type: GrantFiled: May 23, 2017Date of Patent: January 1, 2019Assignee: SanDisk Technologies LLCInventors: Ali Al-Shamma, Tz-yi Liu
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Publication number: 20180342273Abstract: A calibration circuit coupled to a sense amplifier circuit may be configured to determine a response time of the sense amplifier circuit relative to a pulse sequence. Based on the determined response time, the calibration circuit may be configured to set a level of a biasing current to a desired level in order to control the response time of the sense amplifier circuit.Type: ApplicationFiled: May 23, 2017Publication date: November 29, 2018Applicant: SanDisk Technologies LLCInventors: Ali Al-Shamma, Tz-yi Liu
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Patent number: 9715924Abstract: A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.Type: GrantFiled: October 20, 2016Date of Patent: July 25, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Nima Mokhlesi, Ali Al-Shamma
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Publication number: 20170117036Abstract: A non-volatile storage system includes a plurality of non-volatile memory cells configured to form a monolithic three dimensional memory structure, a plurality of bit lines connected to the memory cells, a plurality of source lines connected to the memory cells, a plurality of bit line drivers connected to the bit lines and a plurality of source line drivers connected to the source lines and the bit lines. The source line drivers apply voltages to the source lines based on bit line voltages.Type: ApplicationFiled: October 20, 2016Publication date: April 27, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Ali Al-Shamma, Nima Mokhlesi
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Publication number: 20170117035Abstract: A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.Type: ApplicationFiled: October 20, 2016Publication date: April 27, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Nima Mokhlesi, Ali Al-Shamma
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Patent number: 9536617Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.Type: GrantFiled: October 30, 2015Date of Patent: January 3, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Ali Al-Shamma, Farookh Moogat, Chang Siau, Grishma Shah, Kenneth Louie, Khanh Nguyen, Kapil Verma
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Publication number: 20160293264Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.Type: ApplicationFiled: October 30, 2015Publication date: October 6, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Ali Al-Shamma, Farookh Moogat, Chang Siau, Grishma Shah, Kenneth Louie, Khanh Nguyen, Kapil Verma