Abstract: Example embodiments include an apparatus and a method for monitoring and reporting on HVAC performance. In an example method, an HVAC system is monitored to detect a plurality of sample intervals during which the HVAC system is active. The plurality of sample intervals may be, for example, a plurality of heating intervals and/or a plurality of cooling intervals. An ambient temperature or other environmental parameter is monitored to determine a change over each of the sample intervals. A sample value is determined for each of the sample intervals, each sample value representing a ratio between a duration of the interval and the temperature change over the course of the respective period. Statistics of the sample values are evaluated and may be used to identify changes in HVAC performance. Analogous methods preformed for periods of HVAC inactivity may be used to detect changes in heat retention performance.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.

Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.

Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.

Abstract: In one embodiment, a method includes: receiving, in a monitor, performance metric information from performance monitors of a processor including at least a first core type and a second core type; storing, by the monitor, an application identifier associated with an application in execution and the performance metric information for the first core type and the second core type, in a table; accessing, by a scheduler, at least one entry of the table associated with a first application identifier, to obtain the performance metric information for the first core type and the second core type; and scheduling, by the scheduler, one or more threads of a first application associated with the first application identifier to one or more of the plurality of cores based at least in part on the performance metric information of the at least one entry. Other embodiments are described and claimed.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

Abstract: Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.

Abstract: Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

Abstract: A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.

Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Abstract: Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

Abstract: Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Abstract: A power management technique is provided that operates with regard to a dynamic sleep threshold voltage. If a device's battery voltage is greater than the dynamic sleep threshold voltage, a voltage rail for the device is collapsed during a sleep mode for the device. Conversely, if the battery voltage is less than the dynamic sleep threshold voltage, the voltage rail is sourced during the sleep mode for the device.

Abstract: A power management technique is provided that operates with regard to a dynamic sleep threshold voltage. If a device's battery voltage is greater than the dynamic sleep threshold voltage, a voltage rail for the device is collapsed during a sleep mode for the device. Conversely, if the battery voltage is less than the dynamic sleep threshold voltage, the voltage rail is sourced during the sleep mode for the device.

Abstract: A method and system for managing electrical current within a portable computing device (“PCD”) includes assigning a priority to two or more communications supported by the PCD. A present level of a power supply for the PCD may be monitored by a communications power (“CP”) manager module. Next, the CP manager module may determine if the two or more communications may be transmitted at the present level of the power supply. If the two or more communications cannot be transmitted at the present level of the power supply, then the CP manager module may determine if a timing of at least one of the communications may be adjusted. The CP manager module may also determine a theoretical power level adjustment for at least one of the communications. The two or more communications may be transmitted with any calculated timing off sets and power level adjustments.

Abstract: Various embodiments in the disclosure provide methods implemented by a processor executing on a mobile communication device to dynamically determining whether the power saved by powering down the RF chain between the end of the last reception activities and the beginning of the next reception activities will exceed the power expended to reinitialize the RF chain's components and registers for the next reception activities. Based on this determination, the device processor may configure the RF chain either to power down fully, as in conventional implementations, or to enter a low-power mode in which power is maintained to the power rails supplying the memory registers storing RF communication data, thereby avoiding the power surge of restarting the registers and part of the power drain associated with writing the communication data back into the registers. In some embodiments, the mobile communication device may be a multi-SIM device.

Abstract: Apparatus and methods for power control management in a user equipment (UE) include establishing a first call and a second call at the UE, wherein the first call is associated with a first subscription and the second call is associated with a second subscription. Further, the apparatus and methods include determining concurrency of the first call and the second call. The apparatus and methods also includes adjusting a power level or operating frequency associated with at least one UE component based on determining the concurrency of the first call and the second call.