Patents by Inventor Ali Taha

Ali Taha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11886910
    Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 30, 2024
    Assignee: Intel Corporation
    Inventors: Yanru Li, William Zand, Thomas Klingenbrunn, Ali Taha
  • Publication number: 20220413797
    Abstract: A shared mobility vehicle hosts a moving “info kiosk” that provides information assistance to potential passengers (or other individuals) and to on-board passenger. The approach is applicable to human-operated vehicles, and a particularly applicable to autonomous vehicles where no human operator is available to provide assistance.
    Type: Application
    Filed: December 23, 2020
    Publication date: December 29, 2022
    Inventors: Arun Kumar Kallara Rajappan, Obada Ali Taha Alaqtash, Patrick Langer, Daniel Mario Kindermann, Adam Emfield, Nils Lenke
  • Patent number: 11144467
    Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Yanru Li, Ali Taha, Chia-Hung S. Kuo
  • Publication number: 20210200579
    Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: Yanru Li, William Zand, Thomas Klingenbrunn, Ali Taha
  • Publication number: 20210124615
    Abstract: In one embodiment, a method includes: receiving, in a monitor, performance metric information from performance monitors of a processor including at least a first core type and a second core type; storing, by the monitor, an application identifier associated with an application in execution and the performance metric information for the first core type and the second core type, in a table; accessing, by a scheduler, at least one entry of the table associated with a first application identifier, to obtain the performance metric information for the first core type and the second core type; and scheduling, by the scheduler, one or more threads of a first application associated with the first application identifier to one or more of the plurality of cores based at least in part on the performance metric information of the at least one entry. Other embodiments are described and claimed.
    Type: Application
    Filed: October 29, 2020
    Publication date: April 29, 2021
    Inventors: THOMAS KLINGENBRUNN, RUSSELL FENGER, YANRU LI, ALI TAHA, FAROCK ZAND
  • Publication number: 20210116982
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Rahul Khanna, Xin Kang, Ali Taha, James Tschanz, William Zand, Robert Kwasnick
  • Patent number: 10831658
    Abstract: Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 10, 2020
    Assignee: INTEL CORPORATION
    Inventors: Yanru Li, Chia-Hung Kuo, Ali Taha
  • Patent number: 10477575
    Abstract: In embodiments, apparatuses, methods, and storage media may be described for monitoring channel quality of a radio link between a secondary evolved NodeB (SeNB) and a user equipment (UE) in a wireless communication network configured for dual connectivity. In embodiments, the UE may generate one or more indications of a channel quality of the SeNB-UE radio link and forward the indication to the SeNB. Based on the indication, the UE may receive a radio resource control (RRC) message from a master eNB (MeNB) related to the SeNB-UE radio link. Other embodiments may be claimed.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Kathiravetpillai Sivanesan, Ali Taha Koc, Satish C. Jha, Rath Vannithamby
  • Patent number: 10420065
    Abstract: Embodiments of wireless communication devices and method for discontinuous reception (DRX) mode in wireless communication are generally described herein. Some of these embodiments describe a wireless communication device having processing circuitry arranged to determine to use an extended paging discontinuous reception (DRX) value to increase a paging cycle length above a value and select a first periodicity, based on the extended paging DRX value, at which the UE is to perform evaluation of a parameter of a network in which the UE is opera. The wireless communication device may have physical layer circuitry arranged to transmit a message to the network, indicating that the UE desires to perform evaluation of the parameter at the first periodicity. Other methods and apparatuses are also described.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel IP Corporation
    Inventors: Maruti Gupta, Ali Taha Koc, Rath Vannithamby, Satish Chandra Jha
  • Publication number: 20190272236
    Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Yanru Li, Ali Taha, Chia-Hung S. Kuo
  • Publication number: 20190138448
    Abstract: Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Yanru LI, Chia-Hung KUO, Ali TAHA
  • Patent number: 10075953
    Abstract: Embodiments of the present disclosure describe systems and methods for operation of an evolved node B to provide multiple coverage enhancement levels. Various embodiments may include an operational mode configured to provide a first coverage enhancement level associated with user equipments (UEs) that have established communication with the eNB. These embodiments may also include a discovery mode configured to operate at a second coverage enhancement level to discover UEs configured for a higher coverage enhancement level. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Satish C. Jha, Maruti Gupta, Mohammad Mamunur Rashid, Rath Vannithamby, Ali Taha Koc, Kathiravetpillai Sivanesan
  • Patent number: 9998971
    Abstract: Embodiments of wireless communication devices and method for discontinuous reception (DRX) mode in wireless communication are generally described herein. Some of these embodiments describe a wireless communication device having a module to cause the wireless communication device to enter the DRX mode in an operational state of the wireless communication device. The DRX mode may include a DRX cycle having a DRX cycle length. The DRX cycle length may have a value greater than at least four values of DRX cycle lengths supported by an enhanced node-B.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Ali Taha Koc, Satish Chandra Jha, Maruti Gupta, Rath Vannithamby
  • Publication number: 20180160450
    Abstract: In embodiments, apparatuses, methods, and storage media may be described for monitoring channel quality of a radio link between a secondary evolved NodeB (SeNB) and a user equipment (UE) in a wireless communication network configured for dual connectivity. In embodiments, the UE may generate one or more indications of a channel quality of the SeNB-UE radio link and forward the indication to the SeNB. Based on the indication, the UE may receive a radio resource control (RRC) message from a master eNB (MeNB) related to the SeNB-UE radio link. Other embodiments may be claimed.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 7, 2018
    Inventors: KATHIRAVETPILLAI SIVANESAN, ALI TAHA KOC, SATISH C. JHA, RATH VANNITHAMBY
  • Patent number: 9992744
    Abstract: An Evolved Node-B (eNB) to communicate with a User Equipment (UE) on a Long Term Evolution (LTE) network, the eNB comprising: a first logic to determine whether a UE is capable of receiving and transmitting data at substantially the same time or receiving data at two different frequencies at the same time; and a second logic to configure for the UE a Discontinuous Reception (DRX) configuration such that a DRX ON duration overlaps with a discovery opportunity duration (DOD) according to the determination from the first logic. In another example, the eNB comprises: logic to configure for the UE a DRX configuration such that a DRX ON duration window abuts with a DOD window according to the determination from the first logic. In another example, the eNB operable to perform a method comprising: configuring, for a UE, a DRX configuration such that a DRX ON duration overlaps with a DOD.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Satish Chandra Jha, Ali Taha Koc, Kathiravetpillai Sivanesan, Mohammad Mamunur Rashid, Rath Vannithamby
  • Patent number: 9974099
    Abstract: In embodiments, apparatuses, methods, and storage media may be described for monitoring channel quality of a radio link between a secondary evolved NodeB (SeNB) and a user equipment (UE) in a wireless communication network configured for dual connectivity. In embodiments, the UE may generate one or more indications of a channel quality of the SeNB-UE radio link and forward the indication to the SeNB. Based on the indication, the UE may receive a radio resource control (RRC) message from a master eNB (MeNB) related to the SeNB-UE radio link. Other embodiments may be claimed.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Kathiravetpillai Sivanesan, Ali Taha Koc, Satish C. Jha, Rath Vannithamby
  • Patent number: 9949243
    Abstract: Embodiments of user equipment (UE) and methods for application-agnostic discontinuous reception (DRX) triggering are generally described herein. In some embodiments, a UE is configured to monitor buffer status history and traffic activity history, and trigger DRX mode activation based on the buffer status and the traffic activity history. In some embodiments, the UE may determine a probability, based on the buffer status history and the traffic activity history, that a level of traffic activity that cannot be handled during DRX mode would occur. In these embodiments, the UE may trigger DRX mode activation when the probability is below a threshold.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Maruti Gupta, Ali Taha Koc, Rath Vannithamby
  • Patent number: 9891694
    Abstract: A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.
    Type: Grant
    Filed: December 22, 2012
    Date of Patent: February 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Ali Taha, Vipul Gandhi, Phani Babu Giddi
  • Patent number: 9817470
    Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: November 14, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Suresh Sugumar, Jeffrey Gemar, Ali Taha, Amy Derbyshire, Tao Xue, Mohammad Tamjidi, Rajat Mittal
  • Patent number: 9763235
    Abstract: Embodiments described herein relate generally to a reliable delivery of a paging message in a wireless network environment. To prevent the unacceptable delay of delivery of a paging message to a UE, the number of paging opportunities that are to occur during a paging cycle may be increased. The UE may access a lookup table that indicates the paging opportunities for the paging cycle. The paging opportunities may correspond to subframes of the paging frame that include a paging message. The UE may then detect the paging message in a respective subframe of the paging frame that corresponds with a paging opportunity. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: September 12, 2017
    Assignee: Intel IP Corporation
    Inventors: Rath Vannithamby, Satish C. Jha, Ali Taha Koc, Maruti Gupta