Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.

Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.

Abstract: A method and apparatus for releasing a workpiece from a substrate including providing a substrate which is transparent to a predetermined wavelength of electromagnetic radiation; forming, on the substrate, a separation layer which degrades in response to the predetermined radiation; providing the workpiece on the separation layer; and directing the predetermined radiation at the separation layer through the transparent substrate so as to degrade the separation layer and to separate the workpiece from the substrate.

Abstract: A method for completely characterizing coupled transmission lines by short-pulse propagation is described. The complex frequency-dependent propagation matrix, impedance matrix and admittance matrix for a set of n parallel transmission lines can be determined by comparing the properties of two sets of coupled transmission lines of different length. Each transmission line set has two conductors of unequal length and ground conductors to form a coupled transmission line system. Each transmission line set can have uncoupled ends. An input pulse is provided at at least one node of each transmission line set. The complex frequency dependent propagation matrix of each transmission line set is determined by a comparison of the output pulses at the remaining nodes of each transmission line set which involves ratioing to cancel out the effect of the pad-to-probe discontinuity and the uncoupled ends which make it unnecessary to do any embedding.

Abstract: Electrical interconnection structures are described. The electrical interconnection structures are formed by electrically interconnecting in a stack a plurality of discrete substrates. By using a plurality of discrete substrates, a multilayer dielectric/electrical conductor structure can be fabricated from individual discrete substrates each of which can be tested prior to forming a composite stack so that defects in each discrete substrate can be eliminated before inclusion into the stack. Electrical interconnection between adjacent substrate is provided by an array of contact locations on each surface of the adjacent substrates. Corresponding contacts on adjacent substrates are adapted for mutual electrical engagement. Adjacent contact locations can be thermocompression bonded. To reduce the parasitic capacitance and coupled noise between the contact pads and the electrical conductors within the interior of each discrete substrate, the contact pads on each substrate have elongated shape.

Abstract: A method and apparatus for releasing a workpiece from a substrate including providing a substrate which is transparent to a predetermined wavelength of electromagnetic radiation; forming, on the substrate, a separation layer which degrades in response to the predetermined radiation; providing the workpiece on the separation layer; and directing the predetermined radiation at the separation layer through the transparent substrate so as to degrade the separation layer and to separate the workpiece from the substrate.

Abstract: Far-end noise caused by coupling between active and quiet signal lines of wiring planes of an integrated circuit chip or chip carrier is reduced by providing floating crossing lines in wiring layers in an X-Y wiring plane pair.

Abstract: A thin film region 14 of a multichip carrier 10 is provided with at least one fabrication process or tooling monitor for monitoring the quality of the fabrication process during the sequential formation of the layers of the region 14. The process monitor is formed with a desired layer or layers of the thin film region, such as by a photolithographic process. A centrally disposed active wiring region 30 of a layer is surrounded by peripherally disposed fabrication monitor sites 32. The sites 32 can be located such that they do not occupy or interfere with the surface area required for the wiring region 30 while still being disposed near enough to the wiring region such that the electrical and physical characteristics of the thin film is substantially the same. Four different types of thin film fabrication process monitors are disclosed, including a line/via monitor, a dielectric monitor, a laser assisted repair monitor and a laser assisted engineering change monitor.

Abstract: A magnetic bubble domain storage system comprising an array of rows and columns of logical chips are organized into logical half-chips with even numbered bits in one half-chip and odd numbered bits in the other half-chip. Alternating rows of half-chips are used for storing even numbered bits and odd numbered bits, respectively. Each half-chip has its own bubble domain generator, but a common generator current line serves all generators for a row of even half-chips and all generators for a row of odd half-chips. Thus, information is written into even half-chips and odd half-chips at the same time by pulsing the generator current line common to a row of even half-chips and a row of odd half-chips. Each half-chip has a sensing element and all the sensing elements corresponding to a row of half-chips are connected in series.