Patents by Inventor Allahyar Vahidimowlavi
Allahyar Vahidimowlavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948644Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to program each memory cell of a plurality of memory cells whose respective data state is higher than or equal to a first particular data state of a plurality of data states while inhibiting programming of each memory cell of the plurality of memory cells whose respective data state is lower than the first particular data state, and program each memory cell of the plurality of memory cells whose respective data state is lower than or equal to a second particular data state of the plurality of data states after programming each memory cell of the plurality of memory cells whose respective data state is higher than or equal to the first particular data state.Type: GrantFiled: December 20, 2021Date of Patent: April 2, 2024Assignee: Lodestar Licensing Group LLCInventors: Vishal Sarin, Allahyar Vahidimowlavi
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Publication number: 20220115071Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to program each memory cell of a plurality of memory cells whose respective data state is higher than or equal to a first particular data state of a plurality of data states while inhibiting programming of each memory cell of the plurality of memory cells whose respective data state is lower than the first particular data state, and program each memory cell of the plurality of memory cells whose respective data state is lower than or equal to a second particular data state of the plurality of data states after programming each memory cell of the plurality of memory cells whose respective data state is higher than or equal to the first particular data state.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 11222699Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses.Type: GrantFiled: September 2, 2020Date of Patent: January 11, 2022Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Publication number: 20210241832Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) upon the selected wordline reaching the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: ApplicationFiled: April 23, 2021Publication date: August 5, 2021Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Patent number: 11004513Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: GrantFiled: January 27, 2020Date of Patent: May 11, 2021Assignee: Micron Technology, Inc.Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Publication number: 20200402585Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 10770145Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.Type: GrantFiled: March 11, 2019Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Publication number: 20200185033Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: ApplicationFiled: January 27, 2020Publication date: June 11, 2020Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Patent number: 10546641Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: GrantFiled: December 7, 2018Date of Patent: January 28, 2020Assignee: Micron Technology, Inc.Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Publication number: 20190206485Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 10249365Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.Type: GrantFiled: December 5, 2017Date of Patent: April 2, 2019Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 10049759Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.Type: GrantFiled: February 27, 2017Date of Patent: August 14, 2018Assignee: Intel CorporationInventors: Kalyan Kavalipurapu, Allahyar Vahidimowlavi, Erwin Yu
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Publication number: 20180096722Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.Type: ApplicationFiled: December 5, 2017Publication date: April 5, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 9858991Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.Type: GrantFiled: October 7, 2016Date of Patent: January 2, 2018Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 9842655Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.Type: GrantFiled: December 8, 2015Date of Patent: December 12, 2017Assignee: Intel CorporationInventors: Kalyan Kavalipurapu, Allahyar Vahidimowlavi, Erwin Yu
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Publication number: 20170169896Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Applicant: Intel CorporationInventors: Kalyan Kavalipurapu, Allahyar Vahidimowlavi, Erwin Yu
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Publication number: 20170162272Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.Type: ApplicationFiled: December 8, 2015Publication date: June 8, 2017Applicant: Intel CorporationInventors: Kalyan Kavalipurapu, Allahyar Vahidimowlavi, Erwin Yu
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Publication number: 20170025170Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 9502101Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.Type: GrantFiled: May 29, 2015Date of Patent: November 22, 2016Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 9443610Abstract: A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and a node. The amplifier has a first input, a second input, and an output, the amplifier to receive a second reference voltage on the first input and a sample voltage on the second input. The second switch is electrically coupled between the output of the amplifier and the second input of the amplifier. The capacitor is electrically coupled between the second input of the amplifier and the node. The first switch and the second switch are closed to initialize the node to the first reference voltage and to initialize the amplifier in unity-gain configuration. The first switch and the second switch are opened to detect a leakage current by sensing a change in the sample voltage.Type: GrantFiled: June 4, 2015Date of Patent: September 13, 2016Assignee: Micron Technology, Inc.Inventors: Feng Pan, Shigekazu Yamada, Allahyar Vahidimowlavi, Jae-Kwan Park, Cairong Hu, Kalyan Kavalipurapu