Patents by Inventor Allahyar Vahidimowlavi
Allahyar Vahidimowlavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9443610Abstract: A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and a node. The amplifier has a first input, a second input, and an output, the amplifier to receive a second reference voltage on the first input and a sample voltage on the second input. The second switch is electrically coupled between the output of the amplifier and the second input of the amplifier. The capacitor is electrically coupled between the second input of the amplifier and the node. The first switch and the second switch are closed to initialize the node to the first reference voltage and to initialize the amplifier in unity-gain configuration. The first switch and the second switch are opened to detect a leakage current by sensing a change in the sample voltage.Type: GrantFiled: June 4, 2015Date of Patent: September 13, 2016Assignee: Micron Technology, Inc.Inventors: Feng Pan, Shigekazu Yamada, Allahyar Vahidimowlavi, Jae-Kwan Park, Cairong Hu, Kalyan Kavalipurapu
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Publication number: 20150262657Abstract: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.Type: ApplicationFiled: May 29, 2015Publication date: September 17, 2015Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 9087600Abstract: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.Type: GrantFiled: December 22, 2011Date of Patent: July 21, 2015Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 9025388Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.Type: GrantFiled: October 3, 2013Date of Patent: May 5, 2015Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
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Publication number: 20140043912Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.Type: ApplicationFiled: October 3, 2013Publication date: February 13, 2014Applicant: Micron Technology, Inc.Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
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Patent number: 8553461Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.Type: GrantFiled: August 14, 2012Date of Patent: October 8, 2013Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
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Publication number: 20120307564Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.Type: ApplicationFiled: August 14, 2012Publication date: December 6, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Frankie F. Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
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Patent number: 8243521Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.Type: GrantFiled: December 4, 2009Date of Patent: August 14, 2012Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
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Patent number: 8179724Abstract: Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.Type: GrantFiled: February 18, 2011Date of Patent: May 15, 2012Assignee: Micron Technology, Inc.Inventors: Uday Chandrasekhar, Ebrahim Abedifard, Allahyar Vahidimowlavi
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Publication number: 20120092932Abstract: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.Type: ApplicationFiled: December 22, 2011Publication date: April 19, 2012Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Patent number: 8089805Abstract: Programming a memory in two parts to reduce cell disturb includes, in at least one embodiment, programming data in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.Type: GrantFiled: November 20, 2008Date of Patent: January 3, 2012Assignee: Micron Technology, Inc.Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Publication number: 20110149660Abstract: Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.Type: ApplicationFiled: February 18, 2011Publication date: June 23, 2011Inventors: Uday Chandrasekhar, Ebrahim Abedifard, Allahyar Vahidimowlavi
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Publication number: 20110134701Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.Type: ApplicationFiled: December 4, 2009Publication date: June 9, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Frankie F. Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
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Patent number: 7903461Abstract: Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.Type: GrantFiled: September 22, 2008Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventors: Uday Chandrasekhar, Ebrahim Abedifard, Allahyar Vahidimowlavi
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Publication number: 20100124108Abstract: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.Type: ApplicationFiled: November 20, 2008Publication date: May 20, 2010Inventors: Vishal Sarin, Allahyar Vahidimowlavi
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Publication number: 20100074015Abstract: Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.Type: ApplicationFiled: September 22, 2008Publication date: March 25, 2010Inventors: Uday Chandrasekhar, Ebrahim Abedifard, Allahyar Vahidimowlavi
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Patent number: 7054198Abstract: A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated according to a specification where data stored in the boot block can be read as valid data before data stored in other memory blocks can be validly read upon memory activation.Type: GrantFiled: May 16, 2005Date of Patent: May 30, 2006Assignee: Micron Technology, Inc.Inventors: Christophe J. Chevallier, Allahyar Vahidimowlavi
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Publication number: 20050207224Abstract: A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated according to a specification where data stored in the boot block can be read as valid data before data stored in other memory blocks can be validly read upon memory activation.Type: ApplicationFiled: May 16, 2005Publication date: September 22, 2005Inventors: Christophe Chevallier, Allahyar Vahidimowlavi
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Patent number: 6937519Abstract: A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated according to a specification where data stored in the boot block can be read as valid data before data stored in other memory blocks can be validly read upon memory activation.Type: GrantFiled: December 2, 2003Date of Patent: August 30, 2005Assignee: Micron Technology, Inc.Inventors: Christophe J. Chevallier, Allahyar Vahidimowlavi
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Publication number: 20040111554Abstract: A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one additional voltage pump is provided to supply a word line voltage to the remaining memory blocks. The memory device can be operated according to a specification where data stored in the boot block can be read as valid data before data stored in other memory blocks can be validly read upon memory activation.Type: ApplicationFiled: December 2, 2003Publication date: June 10, 2004Applicant: Micron Technology, Inc.Inventors: Christophe J. Chevallier, Allahyar Vahidimowlavi