Abstract: A memory device having a plurality of memory cells that are group into at least two group of cells. Each cell is capable of being programmed in at least two modes. A mode indicator is associated with each group of cells. The mode indicator indicates which programming mode is used to access the cells. The mode indicator is one or more bits and optionally is user selectable.

Abstract: A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within the memory cell. The method includes setting a target number T of piggyback programming pulses for programming each of 2N−1 vt levels of the memory cell, applying T piggyback programming pulses to the memory cell and determining when the highest one of the 2N−1 vt levels is programmed. If it is determined that the highest one of the 2N−1 vt levels is programmed by a number M of piggyback programming pulses that is less than the target number T, then compensating the programming speed of those ones of said T number of piggyback programming pulses subsequent to the Mth piggyback programming pulse.

Abstract: A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within the memory cell. The method includes generating a programming pulse that has a constant magnitude and has a portion that corresponds to one of the 2N voltage levels and programming at least two of the 2N voltage levels with the programming pulse.

Abstract: A method for operating a memory device includes receiving a first page address and extracting a first addressed page defined by the first page address. The method further includes serially accessing the first addressed page, and, during serial access of the first addressed page, broadcasting a next page address to begin extraction of a next addressed page so that serial access of the next addressed page may immediately follow serial access of the first addressed page with no access latency period.

Abstract: A user selectable option to a memory cell, such as a multilevel NAND flash cell, that allows the user to select to optimize programming time or the data integrity. A programmable memory cell can have multiple programming modes. A mode selector can switch the programming of each cell or group of cells between the programming modes. A first programming mode can program the cell with a first programming voltage and maintaining at least a fifty percent of the maximum data margin. A second programming mode can program the cell with a second programming voltage and maintaining at least an eighty five percent of the maximum data margin. The first programming voltage can be greater than the second programming voltage.

Abstract: A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within the memory cell. The method includes setting a target number T of programming pulses for programming each of 2N−1 vt levels of the memory cell, applying T*(2N−1) programming pulses to the memory cell and determining when the highest one of the 2N−1 vt levels is programmed. If it is determined that the highest one of the 2N−1 vt levels is programmed by a number M of programming pulses that is less than the target number T, then compensating the programming speed of those ones of said T*(2N−1)th number of programming pulses subsequent to the Mth programming pulse.

Abstract: A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within the memory cell. The method includes generating a multi-stepped programming pulse having a first stepped portion and a second stepped portion, normalizing a width of the first stepped portion and programming at least two of said 2N voltage levels with the multi-stepped programming pulse.

Abstract: A method for testing a multi-level memory includes storing multi-level data in a plurality of memory cells of the multi-level memory and reading from configure registers initial values of a plurality of performance variables. The performance variables set operating parameters of the multi-level memory. The method further includes during a first test phase operating the multi-level memory at the initial values of the plurality of performance variables and reading program values of the plurality of performance variables. During a second test phase, the multi-level memory is operated at the program values of the plurality of performance variables.

Abstract: Memory cell programming time can be reduced by using a longer initial pulse followed by regular length pulses as needed. Since memory cell programming pulses have raise and fall times, when the voltage applied is less than the programming voltage, and each programming pulse requires a program verify, which increases the programming overhead, replacing the first few regular pulses with a single longer pulse reduces the programming overhead.

Abstract: A memory device having a plurality of memory cells that are group into at least two group of cells. Each cell is capable of being programmed in at least two modes. A mode indicator is associated with each group of cells. The mode indicator indicates which programming mode is used to access the cells. The mode indicator is one or more bits and optionally is user selectable.

Abstract: A multi-level memory includes an array of memory cells accessible through respective word lines and bit lines a control circuit controlling embedded operations of the memory and a read voltage generating circuit to generate a descending staircase read voltage to a word line associated with a selected memory cell under control of the control circuit. The multi-level memory further includes a read circuit including a latch circuit, and a switch circuit responsive to an evaluate/enable signal to selectively store a read state signal in the latch circuit in response to a sense signal generated from application of the descending staircase read voltage to the word line associated with the selected memory cell.

Abstract: A memory device having a plurality of memory cells that are group into at least two group of cells. Each cell is capable of being programmed in at least two modes. A mode indicator is associated with each group of cells. The mode indicator indicates which programming mode is used to access the cells. The mode indicator is one or more bits and optionally is user selectable.

Abstract: Method of storing and retrieving multiple bits of information in a multi-level cell of non-volatile memory including programming a plurality of multi-level memory cells within a programming time target. The multi-level memory cells having at least first, second, third and fourth programming levels. The fourth programming level being the erase state, the first programming level being the programming level furthest from the fourth programming level. The second and third programming levels being within the first and fourth programming levels, includes erasing the plurality of multi-level memory cells. Then, programming a first group of multi-level memory cells with the first programming level with a first programming pulse count having a first pulse width and a first programming voltage. Then, programming a second group of multi-level memory cells with the second programming level with a second programming pulse count having a second pulse width and a second programming voltage.

Abstract: A method of programming a memory cell comprises erasing, programming, and determining the pulse count for one or more memory cells. The memory cell(s) is erased. Then, the memory cell is programmed with a first programming voltage. A first pulse count is determined. The first pulse count indicates the number of programming pulses used to program the memory cell with the first programming voltage. The first pulse count is compared with a target pulse count. The programming voltage is stored if the first pulse count compares with the target pulse count. If the first pulse count fails to compare with the target pulse count, the memory cell(s) is programmed with a second programming voltage and the process is repeated until the pulse count compares with the target pulse count.

Abstract: A method is presented for generating functional tests for a microprocessor having several operating modes and features. A test module template file includes a basic set of instructions required to configure the microprocessor to operate in any one of the several operating modes and with any of the several features enabled. A user modifies a copy of the test module template file to form a test module file which provides a desired operating environment and causes the microprocessor to perform a desired activity and to produce a test result. An assembler takes as input the test module file, along with the contents of any library files to be included, and produces both an assembly code list file and a test code file. The assembly code list file is a computer program listing containing assembly language instructions and data.

Abstract: A method is presented for event-related functional testing of a microprocessor. A model of the microprocessor is adapted to produce a trigger event, perform a target activity, and respond to a control signal. The target activity occurs over several system clock signal cycles. A control signal generator receives the trigger event and generates the control signal a selectable number of clock cycles (i.e., a delay time) after the trigger event. A testing program includes a program loop which causes the microprocessor model to produce the trigger event, perform the target activity to produce a test result, and compare the test result to an expected result. The program loop is repeatedly executed until the microprocessor model responds to the control signal during each clock cycle of the target activity. If the test result matches the expected result during each execution of the program loop, the microprocessor properly responds to the control signal during the target activity.

Abstract: An interlaced storage method for storing data in multi-level flash memory cells so that data bits from multiple addresses are encoded and stored in a single flash memory cell, and a method for reading and decoding the stored data. In the method for storing data, the data bit values for each address are multiplied by a weight having a greater value for each successively higher address to provide weighted bit values. The weighted bit values for the same order bits from the addresses are then added together to provide results, each result being programmed as a threshold voltage vt in a flash memory cell. To read the stored data, a weight comparison is set equal to the greatest weight and compared with the vt value in a first pass. If the vt value is equal to the weight comparison value, the data bits represented by the vt value are identified.

Abstract: A linkage arrangement supports an implement such that the implement is movable relative to a support member which is also movable relative to a structure. Movement of the implement and support member is limited by mechanical and/or mechanically operated limits. The linkage mechanism enables an increase in the ability to move and orientate the implement within a limit envelope. In a preferred form, a first linkage arm is pivotably mounted to a prime mover. At a distal end of the first linkage arm an orientation member is pivotably attached, the orientation member pivotably attached to a first limit actuating arm. The rotation of the first linkage arm causes rotation of the orientation member. The orientation member provides a base for the attachment of a further arm or implement. The first arm or implement is prevented from contacting the prime mover by the limits provided by the orientation member.