Abstract: A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench isolations (STIs) on the semiconductor substrate, forming a photoresist mask over the STIs, selectively etching the STIs to form curved surface area profiles, growing a layer of tunnel oxide (TOX) over exposed areas of the semiconductor substrate, forming a first polysilicon (poly) layer over the TOX layer and the STIs, chemical-mechanical polishing (CMP) the first poly layer, forming an oxide-nitride-oxide (ONO) layer over the first poly layer, and forming a second poly layer over the ONO layer.

Abstract: For fabrication of a vertical field effect transistor structure for each of an array of flash memory cells for a non-volatile memory device, an opening is etched though top and bottom layers of doped insulating material and a layer of dummy material formed between the bottom and top layers of doped insulating material. The opening is filled with a semiconductor material to form a semiconductor fill. The layer of dummy material is etched away such that a channel region of the semiconductor fill is exposed. A tunnel gate dielectric is formed on the channel region of the vertical field effect transistor. A floating gate electrode material is deposited to abut the tunnel gate dielectric. The tunnel gate dielectric and the floating gate electrode material are disposed on a plurality of planes of the channel region of the vertical field effect transistor. Dopant diffuses from the top and bottom layers of doped insulating material into the semiconductor fill to form drain and source extension junctions.

Abstract: A method and semiconductor wafer is provided for measurement and recordation of hydrophilic elements in semiconductor insulators by depositing a moisture barrier layer over a previously deposited insulating layer of a semiconductor wafer. The semiconductor wafers become pilot or calibration wafers which may be placed immediately in an infrared radiation instrument to allow measurement of the concentration of hydrophilic elements in the insulating layer or stored for recordation purposes and measured later.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.

Abstract: A method of manufacturing and inspecting semiconductor devices wherein defects on inspection wafers are tabulated in a stacked defect table wherein a defect table for each layer is generated per die number and a calculated cumulative die health statistic using an automatic defect classification system and a kill ratio for each defect. The cumulative die health statistic is carried over to the next defect table generated for the next layer.

Abstract: A method of detecting and pre-classifying cluster type defects in a process for manufacturing semiconductor wafers. At least one inspection wafer is selected from a set of semiconductor wafers being process and the first layer of the set is processed. The first layer is scanned for defect information and it is determined whether a cluster pattern exists and comparing the cluster pattern to patterns stored in a pattern detection and classification register and pre-classifying the cluster pattern if a cluster pattern is detected and updating a defect database with comparison and pre-classification information for the first layer. Repeating the process for the next layer.

Abstract: A method of manufacturing a semiconductor device is provided in which a semiconductor substrate with a dielectric layer has channel and via openings formed in the dielectric layer. A seed layer is formed over the dielectric layer and in the openings followed by a resist over the seed layer. The resist is then removed outside the openings. The seed layer outside the openings, which is not covered by the resist, is removed and the seed layer in the openings remains intact because of the resist in the openings. The resist inside the openings is removed and the seed layer inside the openings is electroless plated to fill the openings and form the channels and vias for interconnecting the semiconductor device.

Abstract: A method of manufacturing semiconductor wafers in a processing tool in which it is determined whether the tool has been on idle beyond a predetermined period of time. If the tool has not been on idle beyond the predetermined period of time, a product wafer is automatically processed. If the tool has been on idle beyond the predetermined period of time, a conditioning wafer is automatically processed.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer, forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles.

Abstract: A method of manufacturing semiconductor wafers using electroless plating processing. A partially completed semiconductor wafer having trenches and vias formed in a layer of interlayer dielectric has a barrier layer globally formed on the surface of the partially completed semiconductor wafer. A seed layer is globally formed on the surface of the barrier layer. The barrier and seed layers are removed from portions of the surface of the partially completed semiconductor wafer on which plating is not to occur. The partially completed semiconductor wafer is then subjected to an electroless plating process and conductive material is plated on those portions of the seed layer that remains on the partially completed semiconductor wafer.

Abstract: A method of manufacturing semiconductor devices wherein defects on each layer of a semiconductor wafer are determined to be killer or non-killer defects by correlating critical area information on a die with defect size and classification information. The killer/non-killer defect information is tabulated in a defect table from which statistical yield predictions can be made.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.

Abstract: A method of manufacturing a semiconductor device including selecting at least one die on at least one wafer in a manufacturing lot of wafers to scan and inspect, processing the wafers through a first process, mapping detected defects with the at least one die selected to be scanned and inspected and determining if the selected at least one die should be scanned and inspected in the next process. If it is determined that the selected at least one die should not be scanned and inspected in the next process, at least one alternative die is selected to be scanned and inspected in the next process.

Abstract: A method of manufacturing a semiconductor device having rectangular cross-sectional interfaces between a conductive line and a conductive via. A first layer of photoresist is patterned to expose portions of the semiconductor device under which conductive wires and combination conductive wires and vias are to be formed. A second layer of photoresist is patterned to expose portions of the semiconductor device under which combination conductive wires and vias are to be formed. A second layer of interlayer dielectric in which conductive wires are to be formed and a first layer of interlayer dielectric in which conductive vias are to be formed are simultaneously anisotropically etched to form cavities, which are simultaneously filled with a conductive material.

Abstract: A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.

Abstract: A method of analyzing defects in a semiconductor manufacturing process by removing position offset of a selected scanning tool from the defect location information and adding position offset of a selected review analysis tool. The resulting defect location information from a scanner is based upon a true xy coordinate system and the analysis review tool reviews defect locations based upon its xy coordinate system.

Abstract: A method of manufacturing a semiconductor device having metal structures formed on a first layer of interlayer dielectric, wherein the metal structures have a layer of TiN formed on the surface of the metal structures, a second layer of interlayer dielectric formed on and around the metal structures and layer of TiN, and a layer of photoresist formed on a surface of the second layer of interlayer dielectric. The method includes patterning and developing the layer of photoresist over selected metal structures exposing selected portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are etched down to a surface of the layer of TiN and the layer of TiN is then etched down to the surface of the metal structure.

Abstract: A method of manufacturing a semiconductor device having self-aligned extension junctions and a reduced gate channel length by etching an opening in a layer of phosphoro silicate glass that has been deposited on a substrate. The layer of phosphoro silicate glass serves as a self-aligned solid diffusion source to form LDD extensions. Spacers are formed on the walls of the opening in the phosphoro silicate glass and serve to reduce the length of the gate channel. A gate structure is formed by depositing a layer of gate oxide in the opening in the layer of phosphoro silicate glass and a layer of polysilicon is formed over the layer of gate oxide.

Abstract: A method of manufacturing semiconductor devices wherein defect images are isolated from reference images in an optical tool. Each layer of a semiconductor are inspected for defects and identified defect images are subtracted from reference images providing an operator of the optical tool a resultant image of the defects or a highlighted image of the defect.

Abstract: A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The matrices in the array start with a size approximately double the minimum dimension of vias in the wafer and decrement in size to a size approximately half the minimum dimension.