Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections.

Abstract: A method of reviewing classification data and image data for defects detected in a series of semiconductor manufacturing processes. An inspection wafer is selected from a production lot of wafers and is inspected after the completion of each of the series of semiconductor manufacturing processes. The classification data for each defect is sent to a defect management system and an image for selected defects is sent to an image storage system. Identification data is sent to the defect management system and the image storage system. The image storage system sends a cookie to the defect management system allowing the defect management system to identify defects having an image. A operator controlled review station allows an operator to select defects for review that have an image available for review.

Abstract: A method of manufacturing semiconductor devices wherein images of non-defect anomalies are captured and stored with image data and linkage data in a database. The non-defect anomaly data is stored in database for later retrieval.

Abstract: A method of manufacturing a semiconductor wafer wherein each layer to be scanned is scanned in a scan tool after determination of whether the current recipe is contained in the scan tool. The recipe in the scan tool is compared to the current recipe stored in a server. If the recipe in the scan tool is not the current recipe the current recipe is loaded into the scan tool from the server. The recipes in the server are updated from associated scan tools.

Abstract: A method of manufacturing a semiconductor device with dual damascene structures. A first and second layer of interlayer dielectric separated by a first layer of etch stop material is formed on the surface of a semiconductor substrate on and in which active devices have been formed. A second layer of an etch stop material is formed on the surface of the second layer of interlayer dielectric. A layer of photoresist is formed on the second layer of etch stop material and is patterned and etched to expose portions of the second etch stop material. The exposed portions of the second etch stop material are anisotropically etched exposing portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are first anisotropically etched and then isotropically etched. The etch stop layer between the first and second interlayer dielectric is anisotropically etched and the first layer of interlayer dielectric is anisotropically etched.

Abstract: A method of manufacturing a semiconductor device having multiple layers of interconnects that are filled in a single conductive material filling step. Two layers of interlayer dielectric separated by an etch stop layer are formed over a layer including metal structures in contact with electrodes of active devices formed in and on a semiconductor substrate. A layer of photoresist is formed on a second etch stop layer formed on the upper layer of interlayer dielectric. The layer of photoresist is patterned and etched. Masking and etching processes form openings in the first and second layers of interlayer dielectric including openings to the metal structures. The openings are filled in a single conductive material filling step.

Abstract: A method of manufacturing semiconductor devices wherein a partially completed semiconductor device having a first and second layer of interlayer dielectric and a first and second etch stop layer has the second etch stop layer masked and etched with an etch pattern having dimensions of the trench structure to be formed in the second interlayer dielectric. The second layer dielectric and first etch stop layer are then masked and etched with an etch pattern having dimensions of the via structure to be formed in the first interlayer dielectric. The remaining portions of the photoresist is removed and exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric are then etched simultaneously. The via structure and trench structure are then simultaneously filled with a conductive material.

Abstract: A multiple chip hybrid package using bump technology having multiple chips electrically connected using a flip chip technology such as solder bump technology. Portion of at least one chip is electrically connected to electrical leads connecting terminals inside the package to pins outside the package.

Abstract: A method of filling trenches in a semiconductor wafer with a conductive material is disclosed by selectively electroplating the semiconductor wafer. The trenches are lined with a barrier layer and a seed layer and the semiconductor wafer is submerged in a solution having ions of the selected conductive material. An electrical potential is applied to the electroplating solution and the semiconductor wafer. The seed layer in the trench causes the conductive material ions to be plated in the trench.

Abstract: A multichip integrated semiconductor device having a portion of a first chip bonded to electrical leads in a package using a flip chip technology such as solder bump technology and a second chip bonded to a second portion of the first chip using a flip chip technology such as solder bump technology.

Abstract: A method of using universal alignment marks on a semiconductor wafer that allows the accurate alignment of scanning and analysis tools in relation to the semiconductor wafer. The information in the universal alignment marks are utilized by a vendor generated algorithm incorporated into the respective scanning or analysis tools to accurately position the tool in relation to the semiconductor wafer.

Abstract: A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench.

Abstract: A method of manufacturing a semiconductor device including a step of filling crevices or non-level regions formed during the manufacture of the semiconductor device with a spin-on dielectric material. The spin-on dielectric material prevents conductive material from filling the crevices and causing the device to fail.

Abstract: An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and the second mask layer are patterned to form first gate mask and second gate mask respectively. The polysilicon gate is then formed by anisotropically etching the polysilicon layer. The second gate mask is then removed. The polysilicon gate is then etched isotropically to reduce its width using the gate oxide layer and the patterned first gate mask as hard masks. The first gate mask is then used as a mask for dopant implantation to form source and drain extensions which are spaced away from the edges of the polysilicon gate. Thereafter, the first gate mask is removed and a spacer is formed dopant implantation to form deep source and drain junctions.

Abstract: Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.