Patents by Inventor Allen W. Hanson

Allen W. Hanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296452
    Abstract: Extrinsic structure that is formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. Extrinsic structure is described that can reduce gate leakage current in transistors by over four orders of magnitude.
    Type: Application
    Filed: August 6, 2019
    Publication date: September 23, 2021
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Allen W. Hanson, Chuanxin Lian, Wayne Mack Struble
  • Patent number: 11018220
    Abstract: Structures and methods for isolating semiconductor devices and improving device reliability under harsh environmental conditions are described. An isolation region may be formed by ion implantation in a region of semiconductor surrounding a device. The implantation region may extend into streets of a wafer. A passivation layer may be deposited over the implantation region and extend further into the streets than the isolation region to protect the isolation region from environmental conditions that may adversely affect the isolation region.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 25, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Allen W. Hanson, Wayne Mack Struble, John Claassen Roberts
  • Patent number: 10855230
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 1, 2020
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson, Bryan Schwitter, Chuanxin Lian, Rajesh Baskaran, Frank Gao
  • Patent number: 10790787
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 29, 2020
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Simon John Mahon, Allen W. Hanson, Chuanxin Lian, Frank Gao, Rajesh Baskaran, Bryan Schwitter
  • Publication number: 20200144969
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Application
    Filed: August 12, 2019
    Publication date: May 7, 2020
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson, Bryan Schwitter, Chuanxin Lian, Rajesh Baskaran, Frank Gao
  • Publication number: 20200144970
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Application
    Filed: August 12, 2019
    Publication date: May 7, 2020
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson, Chuanxin Lian, Frank Gao, Rajesh Baskaran, Bryan Schwitter
  • Publication number: 20190096743
    Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.
    Type: Application
    Filed: October 19, 2018
    Publication date: March 28, 2019
    Inventors: Allen W. Hanson, Rajesh Baskaran, Timothy E. Boles
  • Publication number: 20190078941
    Abstract: Thermally-sensitive structure and methods for sensing the temperature in a region of a bipolar junction transistor (BJT) during device operation are described. The region may be at or near a region of highest temperature attained in the BJT. Metal resistance thermometry (MRT) can be implemented to assess a peak operating temperature of a BJT.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson
  • Publication number: 20190028066
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson
  • Publication number: 20190028065
    Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: Simon John Mahon, Allen W. Hanson
  • Patent number: 10147642
    Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 4, 2018
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Allen W. Hanson, Rajesh Baskaran, Timothy E. Boles
  • Publication number: 20180308927
    Abstract: Structures and methods for isolating semiconductor devices and improving device reliability under harsh environmental conditions are described. An isolation region may be formed by ion implantation in a region of semiconductor surrounding a device. The implantation region may extend into streets of a wafer. A passivation layer may be deposited over the implantation region and extend further into the streets than the isolation region to protect the isolation region from environmental conditions that may adversely affect the isolation region.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 25, 2018
    Inventors: Allen W. Hanson, Wayne Mack Struble, John Claassen Roberts
  • Patent number: 9978858
    Abstract: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Jerry Wayne Johnson, Sameer Singhal, Allen W. Hanson, Robert Joseph Therrien
  • Publication number: 20180122928
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Application
    Filed: September 25, 2017
    Publication date: May 3, 2018
    Applicant: MACOM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, Kevin J. Linthicum, Allen W. Hanson
  • Patent number: 9876082
    Abstract: An apparatus includes a channel layer, a first layer, a hole barrier layer and a second layer. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valence band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally forms a field effect transistor.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 23, 2018
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Allen W. Hanson, Gabriel R. Cueva, Wayne M. Struble, Yan Zhang
  • Patent number: 9773898
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: September 26, 2017
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, Kevin J. Linthicum, Allen W. Hanson
  • Publication number: 20170154989
    Abstract: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron to concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 1, 2017
    Inventors: Jerry Wayne Johnson, Sameer Singhal, Allen W. Hanson, Robert Joseph Therrien
  • Patent number: 9627473
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: April 18, 2017
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, Kevin J. Linthicum, Allen W. Hanson, James W. Cook, Jr.
  • Patent number: 9608102
    Abstract: Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Jerry Wayne Johnson, Sameer Singhal, Allen W. Hanson, Robert Joseph Therrien
  • Publication number: 20170069713
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Applicant: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, Kevin J. Linthicum, Allen W. Hanson, James W. Cook, JR.