Abstract: A method of patterning a layer of dielectric material having a thickness greater than 1,000 Å, and typically a thickness greater than 5,000 Å. The method is particularly useful for forming a high aspect ratio via or a high aspect ratio contact including self-aligned contact structures, where the aspect ratio is typically greater than 3 and the feature size of the contact is about 0.25 &mgr;m or less. In particular, an organic, polymeric-based masking material is used in a plasma etch process for transferring a desired pattern through an underlying layer of dielectric material. The combination of masking material and plasma source gas must provide the necessary high selectivity toward etching of the underlying layer of dielectric material. The selectivity is preferably greater than 3:1, where the etch rate of the dielectric material is at least 3 times greater than the etch rate of the organic, polymeric-based masking material.

Abstract: Copper can be pattern etched in a manner which provides the desired feature dimension and integrity, at acceptable rates, and with selectivity over adjacent materials. To provide for feature integrity, the portion of the copper feature surface which has been etched to the desired dimensions and shape must be protected during the etching of adjacent feature surfaces. This is particularly important for feature sizes less than about 0.5 &mgr;m, where presence of even a limited amount of a corrosive agent can eat away a large portion of the feature.

Abstract: The present invention is a method for removing deposited etch byproducts from surfaces of a semiconductor processing chamber after a copper etch process. The method of the invention comprises the following general steps: (a) an oxidation step, in which interior surfaces of the processing chamber are contacted with an oxidizing plasma; (b) a first non-plasma cleaning step, in which interior surfaces of the processing chamber are contacted with an H+hfac-comprising gas; and (c) a second cleaning step, in which interior surfaces of the processing chamber are contacted with a plasma containing reactive fluorine species, whereby at least a portion of the copper etch byproducts remaining after step (b) are volatilized into gaseous species, which are removed from the processing chamber. The method of the invention is preferably performed at a chamber wall temperature of at least 150° C.

Abstract: A first embodiment of the present invention pertains to a method of patterning a semiconductor device conductive feature while permitting easy removal of any residual masking layer which remains after completion of the etching process. A multi-layered masking structure is used which includes a layer of high-temperature organic-based masking material overlaid by either a patterned layer of inorganic masking material or by a layer of patterned high-temperature imageable organic masking material. The inorganic masking material is used to transfer a pattern to the high-temperature organic-based masking material and is then removed. The high-temperature organic-based masking material is used to transfer the pattern and then may be removed if desired. This method is also useful in the pattern etching of aluminum, even though aluminum can be etched at lower temperatures.

Abstract: An RF plasma reactor for processing a semiconductor wafer in a reactor chamber with a multi-radius dome-shaped ceiling and a gas inlet for supplying a process gas into the chamber includes an overhead RF signal applicator near the ceiling for applying an RF signal into the chamber through the ceiling to maintain a plasma of the process gas in the chamber, the plasma having a radial ion density distribution near the plane of the pedestal which is center-high for a greater height of the ceiling above the pedestal and is center-low for a lesser height, the height of the ceiling being intermediate the greater and lesser heights such that the radial ion density distribution is neither center-high nor center-low.

Abstract: The present invention adheres to an optimized coil-domed geometry including a particular dome apex height range relative to the dome base and a particular wafer position range relative to the dome apex.

Abstract: A damascene structure, and a method of fabricating same, containing relatively low dielectric constant materials (e.g., k less than 3.8). A silicon-based, photosensitive material, such as plasma polymerized methylsilane (PPMS), is used to form both single and dual damascene structures containing low k materials. During the manufacturing process that forms the damascene structures, the silicon-based photosensitive material is used as both a hard mask and/or an etch stop.

Abstract: The present disclosure pertains to a method of patterning a semiconductor device feature which provides for the easy removal of any residual masking layer which remains after completion of a pattern etching process. The method provides for a multi-layered masking structure which includes a layer of high-temperature organic-based masking material overlaid by either a layer of a high-temperature inorganic masking material which can be patterned to provide an inorganic hard mask, or by a layer of high-temperature imageable organic masking material which can be patterned to provide an organic hard mask. The hard masking material is used to transfer a pattern to the high-temperature organic-based masking material, and then the hard masking material is removed. The high-temperature organic-based masking material is used to transfer the pattern to an underlying semiconductor device feature.

Abstract: A first embodiment of the present invention pertains to a method of patterning a semiconductor device conductive feature while permitting easy removal of any residual masking layer which remains after completion of the etching process. A multi-layered masking structure is used which includes a layer of high-temperature organic-based masking material overlaid by either a patterned layer of inorganic masking material or by a layer of patterned high-temperature imageable organic masking material. The inorganic masking material is used to transfer a pattern to the high-temperature organic-based masking material and is then removed. The high-temperature organic-based masking material is used to transfer the pattern and then may be removed if desired. This method is also useful in the pattern etching of aluminum, even though aluminum can be etched at lower temperatures.

Abstract: Copper can be pattern etched in a manner which provides the desired feature dimension and integrity, at acceptable rates, and with selectivity over adjacent materials. To provide for feature integrity, the portion of the copper feature surface which has been etched to the desired dimensions and shape must be protected during the etching of adjacent feature surfaces. To avoid the trapping of reactive species interior of the etched copper surface, hydrogen is applied to that surface. Hydrogen is adsorbed on the copper exterior surface and may be absorbed into the exterior surface of the copper, so that it is available to react with species which would otherwise penetrate that exterior surface and react with the copper interior to that surface. Sufficient hydrogen must be applied to the exterior surface of the etched portion of the copper feature to prevent incident reactive species present due to etching of adjacent feature surfaces from penetrating the previously etched feature exterior surface.

Abstract: A method of etching a multicomponent alloy on a substrate, without forming etchant residue on the substrate, is described. In the method, the substrate is placed in a process chamber comprising a plasma generator and plasma electrodes. A process gas comprising a volumetric flow ratio V.sub.r of (i) a chlorine-containing gas capable of ionizing to form dissociated Cl.sup.+ plasma ions and non-dissociated Cl.sub.2.sup.+ plasma ions, and (ii) an inert gas capable of enhancing dissociation of the chlorine-containing gas, in introduced into the process chamber. The process gas is ionized to form plasma ions that energetically impinge on the substrate by (i) applying RF current at a first power level to the plasma generator, and (ii) applying RF current at a second power level to the plasma electrodes. The combination of (i) the volumetric flow ratio V.sub.r of the process gas and (ii) the power ratio P.sub.

Abstract: An inductively coupled RF plasma reactor for processing semiconductor wafer includes a reactor chamber having a side wall and a ceiling, a wafer pedestal for supporting the wafer in the chamber, an RF power source, apparatus for introducing a processing gas into the reactor chamber, and a coil inductor adjacent the reactor chamber connected to the RF power source, the coil inductor including (a) a side section facing a portion of the side wall and including a bottom winding and a top winding, the top winding being at a height corresponding at least approximately to a top height of the ceiling, and (b) a top section extending radially inwardly from the top winding of the side section so as to overlie at least a substantial portion of the ceiling. The present invention adheres to an optimized coil-dome geometry including a particular dome apex height range relative to the dome base and a particular wafer position range relative to the dome apex.

Abstract: An inductively coupled RF plasma reactor for processing semiconductor wafer includes a reactor chamber having a side wall and a ceiling, a wafer pedestal for supporting the wafer in the chamber, an RF power source, apparatus for introducing a processing gas into the reactor chamber, and a coil inductor adjacent the reactor chamber connected to the RF power source, the coil inductor including (a) a side section facing a portion of the side wall and including a bottom winding and a top winding, the top winding being at a height corresponding at least approximately to a top height of the ceiling, and (b) a top section extending radially inwardly from the top winding of the side section so as to overlie at least a substantial portion of the ceiling.