Patents by Inventor Alois Gutmann
Alois Gutmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9401322Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: July 25, 2011Date of Patent: July 26, 2016Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 9373717Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.Type: GrantFiled: December 9, 2014Date of Patent: June 21, 2016Assignee: Infineon Technologies AGInventors: Alois Gutmann, Roland Hampp, Scott Jansen
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Publication number: 20150137253Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.Type: ApplicationFiled: December 9, 2014Publication date: May 21, 2015Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
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Patent number: 8907444Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.Type: GrantFiled: January 25, 2013Date of Patent: December 9, 2014Assignee: Infineon Technologies AGInventors: Alois Gutmann, Roland Hampp, Scott Jansen
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Patent number: 8715909Abstract: Multi-beam lithography systems and methods of manufacturing semiconductor devices using the same are disclosed. For example, the method utilizes non-coincidence of boundaries of electrical fields emanating from chrome on glass or phase shifted mask features distributed over two masks for the optimization of lithographic process windows, side lobe suppression, or pattern orientation dependent process window optimization employing one mask with polarization rotating film on the backside.Type: GrantFiled: October 5, 2007Date of Patent: May 6, 2014Assignee: Infineon Technologies AGInventors: Alois Gutmann, Henning Haffner, Sajan Marokkey, Chandrasekhar Sarma, Roderick Koehle
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Patent number: 8697339Abstract: Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.Type: GrantFiled: April 6, 2011Date of Patent: April 15, 2014Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Infineon Technologies AGInventors: Haoren Zhuang, Chong Kwang Chang, Alois Gutmann, Jingyu Lian, Matthias Lipinski, Len Yuan Tsou, Helen Wang
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Patent number: 8377800Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.Type: GrantFiled: April 23, 2012Date of Patent: February 19, 2013Assignee: Infineon Technologies AGInventors: Sajan Marokkey, Chandrasekhar Sarma, Alois Gutmann
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Patent number: 8361879Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.Type: GrantFiled: May 19, 2008Date of Patent: January 29, 2013Assignee: Infineon Technologies AGInventors: Alois Gutmann, Roland Hampp, Scott Jansen
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Patent number: 8349528Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.Type: GrantFiled: June 20, 2011Date of Patent: January 8, 2013Assignee: Infineon Technologies AGInventors: Matthias Lipinski, Alois Gutmann, Jingyu Lian, Chandrasekhar Sarma, Haoren Zhuang
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Publication number: 20120208341Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.Type: ApplicationFiled: April 23, 2012Publication date: August 16, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Sajan Marokkey, Chandrasekhar Sarma, Alois Gutmann
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Patent number: 8236699Abstract: A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.Type: GrantFiled: February 7, 2011Date of Patent: August 7, 2012Assignees: Infineon North, Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AGInventors: Byung-Goo Jeon, Sung-Chul Park, Nikki Edleman, Alois Gutmann, Fang Chen
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Patent number: 8183129Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.Type: GrantFiled: January 26, 2010Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Sajan Marokkey, Chandrasekhar Sarma, Alois Gutmann
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Patent number: 8148235Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: November 13, 2009Date of Patent: April 3, 2012Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 8138055Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.Type: GrantFiled: August 4, 2010Date of Patent: March 20, 2012Assignees: Infineon Technologies AG, Chartered Semiconductor Manufacturing, Ltd.Inventors: Jin-Ping Han, Alois Gutmann, Roman Knoefler, Jiang Yan, Chris Stapelmann, Jingyu Lian, Yung Fu Chong
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Patent number: 8071261Abstract: Lithography masks and methods of manufacture thereof are disclosed. For example, a method of manufacturing a lithography mask includes forming a stack over a substrate. The stack includes bottom attenuated phase shift material layers, intermediate opaque material layers, and finally top resist layers. The method further includes patterning the stack and then trimming the resist layers to uncover a portion of the opaque material layers. The uncovered opaque material layers are subsequently etched followed by removal of any remaining resist layers.Type: GrantFiled: July 20, 2007Date of Patent: December 6, 2011Assignee: Infineon Technologies AGInventors: Alois Gutmann, Sajan Marokkey, Henning Haffner, Chandrasekhar Sarma, Haoren Zhuang, Matthias Lipinski
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Publication number: 20110278730Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: ApplicationFiled: July 25, 2011Publication date: November 17, 2011Applicant: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann
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Publication number: 20110250530Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.Type: ApplicationFiled: June 20, 2011Publication date: October 13, 2011Applicant: Infineon Technologies AGInventors: Matthias Lipinski, Alois Gutmann, Jingyu Lian, Chandrasekhar Sarma, Haoren Zhuang
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Patent number: 8013364Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: October 15, 2009Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 8007985Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.Type: GrantFiled: January 30, 2006Date of Patent: August 30, 2011Assignee: Infineon Technologies AGInventors: Matthias Lipinski, Alois Gutmann, Jingyu Lian, Chandrasekhar Sarma, Haoren Zhuang
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Patent number: 7998869Abstract: A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.Type: GrantFiled: October 31, 2008Date of Patent: August 16, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Goo Jeon, Sung-Chul Park, Nikki Edleman, Alois Gutmann, Fang Chen