Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

Abstract: In a method of forming a semiconductor device, a wafer includes a first semiconductor region of a first crystal orientation and a second semiconductor region of a second crystal orientation. Insulating material is formed over the wafer. A first portion of the insulating material is removed to expose the first semiconductor region and a second portion of the insulating material is removed to expose the second semiconductor region.

Abstract: A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.

Abstract: Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS) to form a layer of O3-TEOS on the substrate, and treating the layer of O3-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O3-TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the O3-TEOS layer, which can also increase reliability of the device.

Abstract: Process control systems and methods for semiconductor device manufacturing are disclosed. A plurality of feedback and feed-forward loops are used to accurately control the critical dimension (CD) of features formed on material layers of semiconductor devices. Semiconductor devices with features having substantially the same dimension for each die across the surface of a wafer may be fabricated using the novel process control systems and methods described herein.

Abstract: Method for fabricating semiconductor devices with high-K materials without the presence of undesired formations of the high-K material. A preferred embodiment comprises forming a layer of material over a layer of a high-K material, etching the layer of material to expose a portion of the high-K material, performing a CDE (Chemical Downstream Etch) to remove any residual material formed during the etching, and etching the layer of the high-K material into alignment with remaining portions of the layer of material. The removal of the residual material results in a predictable trimming of the high-K material so that the semiconductor device has predictable and consistent performance, which is not possible if the high-K material has unpredictable dimensions.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.

Abstract: Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.

Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Abstract: A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.

Abstract: A method and mask to improve measurement of alignment marks is disclosed. An exemplary embodiment of the invention includes a resist mask with a patterned alignment mark comprising an assemblage of features whose spacing is smaller than the wavelength of light used to measure the alignment. In a preferred embodiment, an alignment mark patterning process alters the appearance of the alignment mark and renders an enhanced contrast with the substrate background.

Abstract: A semiconductor wafer comprises a semiconductor substrate, a surface alignment mark visible on the semiconductor surface and a plurality of nanostructures on the surface of the surface alignment mark having an average pitch adapted to reduce reflectivity of the surface alignment mark in a predetermined light bandwidth.

Abstract: A method and mask to improve measurement of alignment marks is disclosed. An exemplary embodiment of the invention includes a resist mask with a patterned alignment mark comprising an assemblage of features whose spacing is smaller than the wavelength of light used to measure the alignment. In a preferred embodiment, an alignment mark patterning process alters the appearance of the alignment mark and renders an enhanced contrast with the substrate background.

Abstract: A semiconductor wafer comprises a semiconductor substrate, a surface alignment mark visible on the semiconductor surface and a plurality of nanostructures on the surface of the surface alignment mark having an average pitch adapted to reduce reflectivity of the surface alignment mark in a predetermined light bandwidth.

Abstract: A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122). The assist lines (124) reduce the diffraction effects of the lithographic process, resulting in improved depth of focus and resolution of patterns on a semiconductor wafer.

Abstract: A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122). The assist lines (124) reduce the diffraction effects of the lithographic process, resulting in improved depth of focus and resolution of patterns on a semiconductor wafer.

Abstract: A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the indentation. The cavity may be either a trench or a via. A “Trench First” approach and a “Via First” approach are described.

Abstract: In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable pieces of components of the photoresist material, Blob Defects, remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of introducing a low level uniform flood exposure of light in addition to the commonly used exposure to patterned light, followed by standard development. The flood exposure is in the range of 5 to 50% of the dose-to-clear for a non-patterned exposure.

Abstract: A photoresist system is provided that is easily structurable and is suitable for deep ultraviolet range patterning. An increased etching resistance to oxygen-containing plasma is produced in a lithographically generated photoresist structure by treatment with an etch protectant. The etch protectant includes a silylating agent for chemical reaction with reactive groups of the photoresist. In an embodiment, the photoresist includes a base resin initially containing no aromatic groups. Silylating agents include silicon tetrachloride, silicon tetrafluoride, trichlorosilane, dimethylchlorosilane and hexamethyldisilazane.

Abstract: In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable remnants (denoted as Blob Defects) of various components of photoresist material remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of using a Puddle Development technique to develop the photoresist material, and subsequently exposing the semiconductor wafer to at least one Puddle Rinse cycle which uses water.