Patents by Inventor Alon Saado
Alon Saado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8681786Abstract: The invention relates to an internet application flow rate identification method based on message sampling and application signing, comprising the following steps: firstly, message sampling capture: in accordance with sampling strategy and sampling rate the message is captured and decoded; secondly, decoding: the flow information and application data of the message is analyzed by decoding the message; thirdly, flow classification: according to the flow information of the message, a flow state table is found and maintained; fourthly, flow state distinguishing: the signature is matched if the application type of the flow state found through the flow classification is unknown; finally, signature matching: according to the application signature bank, the application data of the message is matched, if matched successfully, the application type of the flow state is updated, and the flow information and application type of that data stream is output.Type: GrantFiled: February 8, 2010Date of Patent: March 25, 2014Assignee: Via Telecom Co., Ltd.Inventors: Qiang Shen, Tarun Tandon, Alon Saado
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Publication number: 20110194555Abstract: A receiver for maintaining parameters of packets received from a transmitter is provided. In the receiver: a first module receives packets from the transmitter and decodes the packets to obtain corresponding payload data, wherein each received packet is transmitted in accordance with a first set of parameters predetermined before decoding of the packets, a second set of parameters which are dynamically determined when the packets are being decoded, and a third set of parameters which are determined after the packets have been decoded. Also, a record generating module generates a record for each received packet, wherein the record comprises the first set, the second set, and the third set of parameters and a buffering module stores the record and corresponding payload data of each received packet. A second module retrieves the record and corresponding payload data from the buffering module, and processes the corresponding payload data according to the record.Type: ApplicationFiled: February 8, 2010Publication date: August 11, 2011Applicant: VIA TELECOM, INC.Inventors: Qiang Shen, Tarun Tandon, Alon Saado
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Patent number: 7680872Abstract: An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.Type: GrantFiled: January 11, 2005Date of Patent: March 16, 2010Assignee: VIA Telecom Co., Ltd.Inventor: Alon Saado
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Patent number: 7644223Abstract: This invention discloses a system comprising a first comparator circuit configured to assert a first control signal in response to a first input number matching one of a first numbers stored therein, a second comparator circuit configured to assert a second control signal in response to: (i) at least one latched assertion of the first control signal; (ii) a second input number matching an intermediate number produced by incrementing the first input number; and (iii) an assertion of an input signal, and to de-assert the second control signal absent of either the matching between the second input number and the intermediate number or the de-assertion of the input signal, and a generator circuit configured to output a predetermined instruction data stored therein in response to the assertion of the first control signal, and to output a third number in response to the assertions of the second control signal.Type: GrantFiled: October 30, 2006Date of Patent: January 5, 2010Assignee: VIA Telecom Co., Ltd.Inventor: Alon Saado
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Patent number: 7613186Abstract: The present invention concerns an apparatus comprising a data unit, a memory and a control unit. The data unit may be configured to generate an output signal comprising a series of frames each having a header and a payload in response to an input signal comprising a series of words. The memory may be configured to hold the output signal and to interface with a device. The control unit may be configured to present one or more control signals configured to control the data unit and the memory.Type: GrantFiled: May 6, 2004Date of Patent: November 3, 2009Assignee: Via Telecom Co., Ltd.Inventor: Alon Saado
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Patent number: 7470849Abstract: A method and system is disclosed for generating one or more predetermined waveforms from one or more contiguous segments of at least one prototype waveform stored in one or more memory tables, the method and system comprising iterations of following sample processing steps: reading at least one sample of the stored prototype waveform at a predetermined address, modifying the sample according to a predetermined logic, and accumulating the modified sample, wherein through a predetermined number of iterations of above steps, a cycle of a new waveform is formed by the accumulated modified samples.Type: GrantFiled: October 4, 2006Date of Patent: December 30, 2008Assignee: VIA Telecom Co., Ltd.Inventors: Alon Saado, Kathy Lieberman, Victor Manzella
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Patent number: 7376152Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data output signal in response to a data input signal, a valid word signal, and a select signal. The second circuit may be configured to generate the select signal in response to the valid word signal, a start of frame signal, and end of frame signal and the data output signal. The select signal may adjust a starting point of each of the words to match a starting point of the first word.Type: GrantFiled: March 30, 2004Date of Patent: May 20, 2008Assignee: VIA Telecom Co., Ltd.Inventor: Alon Saado
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Publication number: 20080112205Abstract: This invention discloses a system comprising a first comparator circuit configured to assert a first control signal in response to a first input number matching one of a first numbers stored therein, a second comparator circuit configured to assert a second control signal in response to: (i) at least one latched assertion of the first control signal; (ii) a second input number matching an intermediate number produced by incrementing the first input number; and (iii) an assertion of an input signal, and to de-assert the second control signal absent of either the matching between the second input number and the intermediate number or the de-assertion of the input signal, and a generator circuit configured to output a predetermined instruction data stored therein in response to the assertion of the first control signal, and to output a third number in response to the assertions of the second control signal.Type: ApplicationFiled: October 30, 2006Publication date: May 15, 2008Inventor: Alon Saado
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Patent number: 7340667Abstract: The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.Type: GrantFiled: May 10, 2004Date of Patent: March 4, 2008Assignee: VIA Telecom Co., Ltd.Inventors: Alon Saado, Muhammad Afsar
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Patent number: 7266756Abstract: The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to read a data signal in response to a read enable signal. The second circuit may be configured to generate the read enable signal. The third circuit may be configured to present the data signal in response to a first state of the read enable signal and present a predetermined value in response to a second state of the read enable signal.Type: GrantFiled: June 25, 2004Date of Patent: September 4, 2007Assignee: VIA Telecom Co., Ltd.Inventors: Alon Saado, Qiang Shen
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Patent number: 7231567Abstract: An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode. The shift mode generally operates with multiple scan clocks that are clocked simultaneously. The capture mode generally operates with multiple scan clocks, but only one of which is toggled at a time.Type: GrantFiled: February 27, 2004Date of Patent: June 12, 2007Assignee: Via Telecom Co., Ltd.Inventors: Alon Saado, Linley Young
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Publication number: 20070079689Abstract: A method and system is disclosed for generating one or more predetermined waveforms from one or more contiguous segments of at least one prototype waveform stored in one or more memory tables, the method and system comprising iterations of following sample processing steps: reading at least one sample of the stored prototype waveform at a predetermined address, modifying the sample according to a predetermined logic, and accumulating the modified sample, wherein through a predetermined number of iterations of above steps, a cycle of a new waveform is formed by the accumulated modified samples.Type: ApplicationFiled: October 4, 2006Publication date: April 12, 2007Inventors: Alon Saado, Kathy Lieberman, Victor Manzella
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Patent number: 7157978Abstract: A lock detector receives a feedback signal from a phase-locked loop and a reference signal. The lock detector includes a first generator for receiving the reference and feedback signals, and for sampling the feedback signal with the reference signal. A second generator is coupled to the first generator for incrementing a count when the feedback signal is at different polarities at consecutive edges of the reference signal. An output line, for asserting a phase lock when the count reaches a defined value, is coupled to the second generator.Type: GrantFiled: April 8, 2005Date of Patent: January 2, 2007Assignee: Via Telecom Co., Ltd.Inventor: Alon Saado
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Publication number: 20060226914Abstract: A lock detector receives a feedback signal from a phase-locked loop and a reference signal. The lock detector includes a first generator for receiving the reference and feedback signals, and for sampling the feedback signal with the reference signal. A second generator is coupled to the first generator for incrementing a count when the feedback signal is at different polarities at consecutive edges of the reference signal. An output line, for asserting a phase lock when the count reaches a defined value, is coupled to the second generator.Type: ApplicationFiled: April 8, 2005Publication date: October 12, 2006Inventor: Alon Saado
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Publication number: 20060155793Abstract: An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.Type: ApplicationFiled: January 11, 2005Publication date: July 13, 2006Inventor: Alon Saado
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Patent number: 7046066Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.Type: GrantFiled: June 15, 2004Date of Patent: May 16, 2006Assignee: Via Telecom Co., Ltd.Inventors: Alon Saado, Linley M. Young, Muhammad Afsar
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Publication number: 20050289432Abstract: The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to read a data signal in response to a read enable signal. The second circuit may be configured to generate the read enable signal. The third circuit may be configured to present the data signal in response to a first state of the read enable signal and present a predetermined value in response to a second state of the read enable signal.Type: ApplicationFiled: June 25, 2004Publication date: December 29, 2005Inventors: Alon Saado, Qiang Shen
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Publication number: 20050275441Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.Type: ApplicationFiled: June 15, 2004Publication date: December 15, 2005Inventors: Alon Saado, Linley Young, Muhammad Afsar
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Publication number: 20050251717Abstract: The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.Type: ApplicationFiled: May 10, 2004Publication date: November 10, 2005Inventors: Alon Saado, Muhammad Afsar
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Publication number: 20050249204Abstract: The present invention concerns an apparatus comprising a data unit, a memory and a control unit. The data unit may be configured to generate an output signal comprising a series of frames each having a header and a payload in response to an input signal comprising a series of words. The memory may be configured to hold the output signal and to interface with a device. The control unit may be configured to present one or more control signals configured to control the data unit and the memory.Type: ApplicationFiled: May 6, 2004Publication date: November 10, 2005Inventor: Alon Saado