Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data output signal in response to a data input signal, a valid word signal, and a select signal. The second circuit may be configured to generate the select signal in response to the valid word signal, a start of frame signal, and end of frame signal and the data output signal. The select signal may adjust a starting point of each of the words to match a starting point of the first word.

Abstract: An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode. The shift mode generally operates with multiple scan clocks that are clocked simultaneously. The capture mode generally operates with multiple scan clocks, but only one of which is toggled at a time.

Abstract: The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.

Abstract: The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.