Patents by Inventor Alper Buyuktosunoglu

Alper Buyuktosunoglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240053897
    Abstract: Various embodiments are provided herein for clearing memory of system in a computing environment. A zero-filled cache line with a single z-bit per entry in the cache directory may be defined. The “z” is a positive integer. A plurality of instruction set architecture (“ISA”) instructions are provided with a single z-bit in a cache line as defined in a cache directory to clear an entire cache line.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent ABALI, Alper BUYUKTOSUNOGLU, Craig R WALTERS, Elpida TZORTZATOS, Bartholomew BLANER
  • Patent number: 11886969
    Abstract: Embodiments of a method are disclosed. The method includes performing distributed deep learning training on a batch of training data. The method also includes determining training times representing an amount of time between a beginning batch time and an end batch time. Further, the method includes modifying a communication aspect of the communication straggler to reduce a future network communication time for the communication straggler to send a future result of the distributed deep learning training on a new batch of training data in response to the centralized parameter server determining that the learner is the communication straggler.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Wei Zhang, Xiaodong Cui, Abdullah Kayi, Alper Buyuktosunoglu
  • Patent number: 11886342
    Abstract: A method, system, and computer program product for augmenting cache replacement operations are provided. The method identifies a set of cache lines within a first cache level of a multilevel cache. A first candidate cache line is identified based on a first replacement scheme of the first cache level. A second candidate cache line is identified based on the first replacement scheme of the first cache level. A replacement cache line is selected for replacement in the first cache level. The replacement cache line is selected from the first candidate cache line and the second candidate cache line and based on the first replacement scheme of the first cache level and a second replacement scheme of a second cache level. The method removes the replacement cache line from the first cache level.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Aaron Dingler, Mohit Karve, Alper Buyuktosunoglu
  • Publication number: 20240028095
    Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 25, 2024
    Inventors: Tobias Webel, Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, Eric Jason Fluhr, IAN KRISPIN CARMICHAEL, Gregory Scott Still
  • Publication number: 20240028447
    Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 25, 2024
    Inventors: Alejandro Alberto Cook Lobo, Andrew A. Turner, CHRISTIAN JACOBI, Eberhard Engler, Edward C. McCain, Kevin P. Low, Phillip John Restle, Pradeep Bhadravati Parashurama, Tobias Webel, Alper Buyuktosunoglu, KARL EVAN SMOCK ANDERSON, Sean Michael Carey, KENNEDY CHERUIYOT, Daniel Kiss, Isidore G. Bendrihem, IAN KRISPIN CARMICHAEL
  • Patent number: 11875256
    Abstract: Embodiments of a method are disclosed. The method includes performing decentralized distributed deep learning training on a batch of training data. Additionally, the method includes determining a training time wherein the learner performs the decentralized distributed deep learning training on the batch of training data. Further, the method includes generating a table having the training time and other processing times for corresponding other learners performing the decentralized distributed deep learning training on corresponding other batches of other training data. The method also includes determining that the learner is a straggler based on the table and a threshold for the training time. Additionally, the method includes modifying a processing aspect of the straggler to reduce a future training time of the straggler for performing the decentralized distributed deep learning training on a new batch of training data in response to determining the learner is the straggler.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Wei Zhang, Xiaodong Cui, Abdullah Kayi, Alper Buyuktosunoglu
  • Publication number: 20240013050
    Abstract: An example system includes a processor to prune a machine learning model based on an importance of neurons or weights. The processor is to further permute and pack remaining neurons or weights of the pruned machine learning model to reduce an amount of ciphertext computation under a selected constraint.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventors: Subhankar PAL, Alper BUYUKTOSUNOGLU, Ehud AHARONI, Nir DRUCKER, Omri SOCEANU, Hayim SHAUL, Kanthi SARPATWAR, Roman VACULIN, Moran BARUCH, Pradip BOSE
  • Patent number: 11847022
    Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: December 19, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Deanna Postles Dunn Berger
  • Patent number: 11836220
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate updating, such as averaging and/or training, of one or more statistical sets are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can include a computing component that averages a statistical set, provided by the system, with an additional statistical set, that is compatible with the statistical set, to compute an averaged statistical set, where the additional statistical set is obtained from a selected additional system of a plurality of additional systems. The computer executable components also can include a selecting component that selects the selected additional system according to a randomization pattern.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: December 5, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiaodong Cui, Wei Zhang, Mingrui Liu, Abdullah Kayi, Youssef Mroueh, Alper Buyuktosunoglu
  • Patent number: 11817697
    Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Adam Benjamin Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Alper Buyuktosunoglu, Tobias Webel, Michael Joseph Cadigan, Jr., Paul Jacob Logsdon, Sean Michael Carey, Stefan Payer, Karl Evan Smock Anderson, Mark Cichanowski
  • Patent number: 11810340
    Abstract: A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached—where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Swagath Venkataramani
  • Patent number: 11797446
    Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Jang-Soo Lee, Deanna Postles Dunn Berger
  • Patent number: 11789518
    Abstract: Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Pradeep Bhadravati Parashurama, Alper Buyuktosunoglu, Ramon Bertran Monfort, Tobias Webel, Srinivas Bangalore Purushotham, Preetham M. Lobo
  • Patent number: 11792303
    Abstract: Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: October 17, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajat Rao, Ashutosh Mishra, Bulent Abali, Alper Buyuktosunoglu
  • Publication number: 20230318286
    Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Inventors: Adam Benjamin COLLURA, Michael ROMAIN, William V. HUOTT, Pawel OWCZARCZYK, Christian JACOBI, Anthony SAPORITO, Chung-Lung K. SHUM, Alper BUYUKTOSUNOGLU, Tobias WEBEL, Michael Joseph CADIGAN, JR., Paul Jacob LOGSDON, Sean Michael CAREY, Stefan PAYER, Karl Evan Smock ANDERSON, Mark CICHANOWSKI
  • Publication number: 20230315627
    Abstract: A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.
    Type: Application
    Filed: March 16, 2022
    Publication date: October 5, 2023
    Inventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Deanna Postles Dunn Berger
  • Publication number: 20230297382
    Abstract: A cache compression predictor can be coupled to a central processing unit (CPU) CPU core. The CPU core can read a cache line from a cache. Upon the CPU core reading the cache line, the cache compression predictor can predict whether the cache line is a compressed cache line or an uncompressed cache line.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Inventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Deanna Postles Dunn Berger
  • Publication number: 20230281077
    Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 7, 2023
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent ABALI, Alper BUYUKTOSUNOGLU, Brian Robert PRASKY, Deanna Postles Dunn BERGER
  • Patent number: 11740933
    Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: August 29, 2023
    Assignee: International Business Machines Corporation
    Inventors: Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Pradip Bose, Robert Matthew Senger, Aporva Amarnath
  • Patent number: 11734084
    Abstract: Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augusto Vega, Alper Buyuktosunoglu, Pradip Bose, Vaidyanathan Srinivasan, Ranjal Gautham Shenoy