Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

Abstract: Embodiments of the present invention include a system, computer-implemented method, and a computer program product. A non-limiting example of the method includes a processor utilizing a model having a plurality of parameters. The processor compares a current value of a model parameter to a prior value of the model parameter. Based at least in part on comparing the current value of the model parameter to the prior value of the model parameter, a determination is made that the model being utilized by the processor has changed. The current value of the model parameter is transmitted by the processor.

Abstract: A power controller that controls power usage of a heterogeneous system is provided. The power controller receives a power usage cap for a heterogeneous system that includes multiple components. The power controller assigns priorities that respectively correspond to the multiple components. The power controller assigns power shifting ratios that respectively correspond to the multiple components. The power controller adjusts a total power usage of the multiple components to be within a threshold of the power usage cap by adjusting the power usage of individual components in a sequence defined by the assigned priorities. The power controller shifts a power usage from a first-priority component to a second-priority component (and so on) according to the assigned power shifting ratios.

Abstract: A computer system that has two or more processing engines (PE), each capable of performing one or more operations on one or more operands but one or more of the PEs performs the operations unreliably. Initial results of each operation are debiased to create a debiased result used by the system instead of the initial result. The debiased result has an expected value equal to a correct output where the correct output is the initial result the respective operation would have produced if the respective operation performed was reliable.

Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.

Abstract: Embodiments for mitigating security vulnerabilities in a heterogeneous computing system are provided. Anomalous cache coherence behavior may be dynamically detected between a host and one or more accelerators using a cache controller at a shared last level cache based upon a pair-based coherence messages functioning as a proxy for indicating one or more security attack protocols.

Abstract: Embodiments for implementing optimized accelerators in a computing environment are provided. Selected instruction sequence code blocks derived from one or more application workloads may be consolidated together to activate one or more accelerators subject to one or more constraints and projections.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.

Abstract: Embodiments for generating representative microbenchmarks in a computing environment are provided. One or more tracing points may be selected in a target application. Executed instructions and used data of the target application may be dynamically traced according to the one or more tracing points according to a tracing plan. Tracing information of the dynamic tracing may be replicated in an actual computing environment and a simulated computing environment.

Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.

Abstract: Embodiments for mitigating cache-based data security vulnerabilities in a computing environment are provided. Cache pollution due to speculative memory accesses within a speculative path is avoided by delaying data updates to a cache and memory subsystem until the speculative memory accesses are resolved. A speculative buffer is used to maintain the speculative memory accesses such that a state of the cache remains unchanged until the speculative memory accesses are committed.

Abstract: Various embodiments are provided for load balancing of machine learning operations in a computing environment by a processor. One or more machine learning operations performing inference or training operations may by dynamically balanced between one or more edge computing devices in a wireless communication network and a cloud computing system for increasing performance of a selected metric.

Abstract: A power controller that controls power usage of a heterogeneous system is provided. The power controller receives a power usage cap for a heterogeneous system that includes multiple components. The power controller assigns priorities that respectively correspond to the multiple components. The power controller assigns power shifting ratios that respectively correspond to the multiple components. The power controller adjusts a total power usage of the multiple components to be within a threshold of the power usage cap by adjusting the power usage of individual components in a sequence defined by the assigned priorities. The power controller shifts a power usage from a first-priority component to a second-priority component (and so on) according to the assigned power shifting ratios.

Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

Abstract: Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.

Abstract: Various embodiments are provided for providing a dynamic random-access memory (“DRAM”) cache as second type memory in a computing system by a processor. A selected amount of bytes in a memory line may be cleared using one or more spare bits of the DRAM, a data compression operation, or a combination thereof. A cache directory and data may be stored in the memory line. The DRAM cache is configured as a cache of a second type memory.

Abstract: A coarse error correction system for detecting, predicting, and correcting errors in neural networks is provided. The coarse error correction system receives a first set of statistics that are computed from values collected from a neural network during a training phase of the neural network. The coarse error correction system computes a second set of statistics based on values collected from the neural network during a run-time phase of the neural network. The coarse error correction system detects an error in the neural network during the run-time phase of the neural network by comparing the first set of statistics with the second set of statistics. The coarse error correction system increases a voltage setting to the neural network based on the detected error.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.