Abstract: During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In one implementation wet-etching and/or sputter etch-back (SEB) is performed prior to applying a reverse-tone mask. In another implementation a wet etching step is performed after the reverse-tone mask is stripped. One significant result of each of these steps is a reduction in the height and width of at least some of the oxide horns that remain after the reverse-tone mask is stripped. As such, the oxide structures that need to be planarized during CMP will be smaller than those of the prior art. Moreover, since the resulting oxide structures that need to be planarized by CMP processing are smaller, the oxide layer can be initially applied at a smaller thickness than that of the prior art.

Abstract: A method for making an integrated circuit preferably includes the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region and to define a recess within the dielectric layer filling the trench to serve as an alignment mark; and polishing the selectively etched dielectric layer and leaving the alignment mark. The method may also include forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step.

Abstract: A non-destructive method for measuring the thickness loss of a polishing pad due to pad conditioning includes the use of rigid planar members placed on the surfaces of both the conditioned and non-conditioned sections of the polishing pad. Measurements are made using measurement instruments which overhang the depressed conditioned section and measure the height difference between the upper surfaces of the planar members. The measurement instruments may be repositioned and measurements repeated to obtain an average thickness loss.

Abstract: A method of making an integrated circuit includes depositing a conductive layer, having conductive lines with gaps therebetween, adjacent a semiconductor substrate. A fluoro-silicate glass (FSG) layer is deposited by high-density plasma chemical vapor deposition (HDP-CVD), over the patterned conductive layer and to fill the gaps between conductive lines. The method further includes chemically mechanically polishing the FSG layer and depositing an undoped oxide layer on the FSG layer. Peaks of the FSG layer which correspond to the widths of the conductive metal lines are reduced by the CMP step. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.

Abstract: Test structures are disclosed for use in a system and with an associated method to test the effectiveness of planarization systems used in the fabrication of semiconductor devices and integrated circuits. A method of creating the test structure utilizes traditional semiconductor fabrication techniques, but uses substantially similar materials, such as oxide, for each of the layers of the test structure. Because the test structure comprises layers of substantially the same material, reliable uniform measurements of the thickness of the test structure may be obtained by an optical metrology tool. These measurements may then be analyzed and displayed in tabular reports or multi-dimensional plots to judge the effectiveness of the planarization system.

Abstract: A method for preparing a chemical mechanical polishing apparatus for polishing product substrates includes polishing designated “warm-up” substrates until polishing pad characteristics have achieved steady state conditions. The reusable warm-up substrates may be formed of a mechanically resistant material or a material having substantially the same removal characteristic as the product film to be polished. The reusable warm-up substrates may also be formed of a mechanically resistant film formed over a semiconductor substrate. The polishing pad characteristic of pad compression may be determined using a previously established correlation or it may be measured.

Abstract: The present invention provides a wafer carrier for use with a semiconductor wafer polishing apparatus. In one embodiment, the wafer carrier comprises a carrying head having opposing first and second surfaces, a primary channel system formed in the second surface, and a secondary channel system formed in the second surface. The first surface is coupleable to the semiconductor polishing apparatus and the second surface is adapted to receive a semiconductor wafer to be polished. The primary channel system comprises first and second intersecting channels. The secondary channel system intersects the primary channel system so that the secondary channel system and the primary channel system cooperate to occupy a substantial portion of a surface area of the second surface. Therefore, the primary channel system and the secondary channel system decrease an amount of force required to remove the semiconductor wafer from the second surface.

Abstract: An integrated circuit includes a conductive layer adjacent a semiconductor substrate. The conductive layer includes conductive lines having gaps therebetween. A fluoro-silicate glass (FSG) layer is over the patterned conductive layer fills the gaps between conductive lines. Also, an undoped oxide layer is on the FSG layer. Peaks of the FSG layer which overlie the conductive metal lines have been reduced by CMP. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.

Abstract: An apparatus and method for performing chemical-mechanical polishing is disclosed in which the pad is secured to the platen without the use of adhesives. A polishing pad and a platen are secured together by a releasable attractive force; the force may comprise a vacuum or electromagnetic force, and the pad has a hard or magnetic backside layer for facing the plating and responding to the attractive force. This invention has particular application to chemical-mechanical polishing for use in planarizing dielectrics.

Abstract: A chemical-mechanical polishing apparatus includes a polishing table having a top surface and an annular trench formed in the top surface and defining an annular configured polishing area in the polishing table. A drive mechanism rotates the polishing table. An annular diaphragm is positioned within the annular configured polishing area and has a top surface and bottom surface. An annular configured polishing pad is positioned on the diaphragm. A fluid actuated pressure mechanism is associated with the annular configured polishing area for exerting pressure upward onto the bottom surface of the annular diaphragm as a polishing table rotates for exerting an upward biasing pressure onto the polishing pad and imparting a desired counter force against any downward pressure exerted against a semiconductor wafer during chemical-mechanical polishing.

Abstract: The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer, backfilling with oxide, and polishing by chemical-mechanical polishing (CMP) to produce a planar, trench isolated, wafer. To ensure planarity of the wafer after CMP, and avoid dishing of the field oxide, a dual silicon nitride polish stop layer is used. The first polish stop layer is applied selectively to protect the active device regions, and the second polish stop layer is applied selectively to protect the field oxide regions.

Abstract: A method of manufacturing integrated circuits utilizing chemical mechanical polishing (CMP) is disclosed. A dielectric layer, illustratively, having a dopant, dye, etc. termed a "marker layer" is formed upon a wafer having partially fabricated integrated circuits thereon. An undoped, undyed layer is deposited upon the marker layer. The undoped or undyed layer is polished and the waste slurry is monitored until a signal indicating the exposure of the signal layer is obtained. Analysis of the signal provides an indication of when the CMP process should be terminated.

Abstract: A method and apparatus for limiting or eliminating the edge effect in a chemical mechanical polishing apparatus comprising a substrate holder and a retaining ring spaced from and around the holder, a rotatable platen and a polishing pad on the platen, by essentially flattening the pad in the area in which it normally tends to deform. The invention is carried out by applying a fluid under pressure, preferably the polishing slurry, to the pad in the region of the gap between the retaining ring and the holder to substantially flatten the pad in the area around the edge of the substrate.

Abstract: The present invention provides a method for polishing a semiconductor substrate having a first layer of material formed on a second layer of different material. In one embodiment, the method includes placing the semiconductor substrate against a polishing surface and polishing the semiconductor substrate, producing a first vibration by polishing and removing the first layer, producing a second vibration by polishing at least a portion of the second layer, and detecting a change from the first vibration to the second vibration with a vibration sensor. The vibration that is sensed in the present invention is physical or mechanical vibration, and it is not a vibration associated with a change in temperature. The vibration sensor may be of varying types. For example, the vibration sensor may be an acoustic sensor or an ultrasonic sensor.

Abstract: An apparatus and method for performing chemical-mechanical polishing is disclosed in which the pad is secured to the platen without the use of adhesives. A polishing pad and a platen are secured together by a releasable attractive force; the force may comprise a vacuum or electromagnetic force, and the pad has a hard or magnetic backside layer for facing the plating and responding to the attractive force. This invention has particular application to chemical-mechanical polishing for use in planarizing dielectrics.

Abstract: The present invention provides a method of forming a opening in a semiconductor dielectric layer. In an advantageous embodiment, the method comprises the steps of forming a hardmask layer on the dielectric layer wherein the hardmask layer has an etch rate less than an etch rate of the dielectric layer, forming a guide opening through the hardmask layer, forming a spacer within the guide opening that reduces a diameter of the guide opening and forming the opening in the dielectric layer through the guide opening. The method may further include the steps of depositing a conductive material in the opening and guide opening and over at least a portion of the hardmask layer that extends beyond the guide opening, and removing the hardmask layer and the conductive material layer that extend beyond the guide opening. In certain embodiments, the contact opening may be formed to a width equal to or less than 0.25 .mu.m.

Abstract: Certain devices require a high quality thin (<25 nanometer) dielectric layer formed on a deposited silicon layer. Applications include capacitor dielectrics in dynamic memories and linear devices. In another application, an electrically erasable programmable read only memory (EEPROM) uses an SiO.sub.2 layer between the write gate and the floating gate. The present technique oxidizes amorphous silicon under conditions that suppress grain growth to produce a higher quality oxide than that achieved with conventional furnace oxidation of polysilicon. Rapid thermal oxidation is one method of practicing the technique.

Abstract: A novel etchant which comprises a mixture of ethylene glycol and hydrofluoric acid, preferably buffered hydrofluoric acid, has been found to control the etch rate of refractory metal silicides, in particular titanium silicide, in a manner such that titanium silicide may be used in place of tantalum silicide for interconnects and gates in semiconductor integrated circuits.