Patents by Inventor Alvin J. Joseph

Alvin J. Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10439053
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Publication number: 20190267304
    Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
  • Publication number: 20190252530
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Patent number: 10367084
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Patent number: 10367083
    Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Renata Camillo-Castillo, Qizhi Liu, John J. Pekarik, Alvin J. Joseph, Peter B. Gray
  • Patent number: 10340352
    Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven M. Shank, Alvin J. Joseph, John J. Ellis-Monaghan
  • Publication number: 20190181250
    Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.
    Type: Application
    Filed: February 18, 2019
    Publication date: June 13, 2019
    Inventors: Vibhor Jain, Renata Camillo-Castillo, Qizhi Liu, John J. Pekarik, Alvin J. Joseph, Peter B. Gray
  • Publication number: 20190139819
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Mark D. JAFFE, Alvin J. JOSEPH, Qizhi LIU, Anthony K. STAMPER
  • Publication number: 20190081597
    Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 14, 2019
    Inventors: Vibhor Jain, Anthony K. Stamper, Alvin J. Joseph, John J. Pekarik
  • Patent number: 10211087
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 10211146
    Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhong-Xiang He, Mark D. Jaffe, Randy L. Wolf, Alvin J. Joseph, Brett T. Cucci, Anthony K. Stamper
  • Publication number: 20190035919
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Patent number: 10157777
    Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhong-Xiang He, Mark D. Jaffe, Randy L. Wolf, Alvin J. Joseph, Brett T. Cucci, Anthony K. Stamper
  • Patent number: 10134880
    Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, Alvin J. Joseph, Pernell Dongmo
  • Publication number: 20180323066
    Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.
    Type: Application
    Filed: May 2, 2017
    Publication date: November 8, 2018
    Inventors: Michel J. Abou-Khalil, Steven M. Shank, Alvin J. Joseph, Michael J. Zierak
  • Publication number: 20180286968
    Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Inventors: Vibhor Jain, Qizhi Liu, Alvin J. Joseph, Pernell Dongmo
  • Publication number: 20180269295
    Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 20, 2018
    Inventors: Steven M. Shank, Alvin J. Joseph, John J. Ellis-Monaghan
  • Patent number: 9917005
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Publication number: 20180068887
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 8, 2018
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 9847415
    Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 19, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan B. Botula, Alvin J. Joseph, Stephen E. Luce, John J. Pekarik, Yun Shi