Abstract: Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

Abstract: Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

Abstract: A design structure for an electrically tunable resistor. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes a resistor including: a first resistive layer; at least one second resistive layer; and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer.

Abstract: A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

Abstract: An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

Abstract: System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.

Abstract: An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

Abstract: An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

Abstract: A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.

Abstract: A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

Abstract: A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

Abstract: System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.

Abstract: An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

Abstract: An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor.

Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

Abstract: A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

Abstract: A magnetic tunnel junction paired to a semiconductor field-effect transistor is described. In one embodiment, there is a circuit that comprises at least one semiconductor field-effect transistor and a magnetic tunnel junction coupled to the at least one semiconductor field-effect transistor. The magnetic tunnel junction has a control line that is configured to control operational characteristics of the at least one semiconductor field-effect transistor.