Patents by Inventor Alvin W. Strong
Alvin W. Strong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7512506Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.Type: GrantFiled: May 31, 2007Date of Patent: March 31, 2009Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Oliver Aubel, Tom C. Lee, Deborah M. Massey, Travis S. Merrill, Stanley W. Polchlopek, Alvin W. Strong, Timothy D. Sullivan
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Patent number: 7511378Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.Type: GrantFiled: May 30, 2006Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Jason P. Gill, David L. Harmon, Deborah M. Massey, Alvin W. Strong, Timothy D. Sullivan, Junichi Furukawa
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Publication number: 20080297188Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Applicants: International Business Machines Corporation, Advanced Micro Devices, Inc. (AMD)Inventors: Oliver Aubel, Tom C. Lee, Deborah M. Massey, Travis S. Merrill, Stanley W. Polchlopek, Alvin W. Strong, Timothy D. Sullivan
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Publication number: 20080237590Abstract: A design structure for an electrically tunable resistor. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes a resistor including: a first resistive layer; at least one second resistive layer; and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer.Type: ApplicationFiled: April 10, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Icko E. T. Iben, Alvin W. Strong
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Publication number: 20080237797Abstract: An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor.Type: ApplicationFiled: March 27, 2007Publication date: October 2, 2008Inventors: ICKO E.T. IBEN, Alvin W. Strong
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Publication number: 20080191314Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.Type: ApplicationFiled: April 18, 2008Publication date: August 14, 2008Applicant: International Busines Machines CorporationInventors: John M. Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Patent number: 7388274Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.Type: GrantFiled: August 15, 2007Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: John M. Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Patent number: 7315075Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.Type: GrantFiled: January 26, 2005Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: John M Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Publication number: 20070268736Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.Type: ApplicationFiled: May 19, 2006Publication date: November 22, 2007Inventors: Ethan H. Cannon, Alvin W. Strong
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Patent number: 7298161Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.Type: GrantFiled: March 24, 2005Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody J. Van Horn, Ernest Y. Wu
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Patent number: 7096450Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.Type: GrantFiled: June 28, 2003Date of Patent: August 22, 2006Assignee: International Business Machines CorporationInventors: Jason P. Gill, David L. Harmon, Deborah M. Massey, Alvin W. Strong, Timothy D. Sullivan, Junichi Furukawa
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Patent number: 7064414Abstract: A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.Type: GrantFiled: November 12, 2004Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: John M Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Patent number: 7023041Abstract: A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.Type: GrantFiled: January 13, 2003Date of Patent: April 4, 2006Assignee: International Business Machines CorporationInventors: Giuseppe La Rosa, Thomas W. Dyer, Oleg Gluschenkov, Jack A. Mandelman, Carl J. Radens, Alvin W. Strong
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Patent number: 6891359Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.Type: GrantFiled: January 24, 2003Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody J. Van Horn, Ernest Y. Wu
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Publication number: 20040262031Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.Type: ApplicationFiled: June 28, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason P. Gill, David L. Harmon, Deborah M. Massey, Alvin W. Strong, Timothy D. Sullivan, Junichi Furukawa
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Publication number: 20040145384Abstract: A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area.Type: ApplicationFiled: January 24, 2003Publication date: July 29, 2004Applicant: International Business Machines CorporationInventors: Kerry Bernstein, Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody J. Van Horn, Ernest Y. Wu
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Publication number: 20040135188Abstract: A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.Type: ApplicationFiled: January 13, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Giuseppe La Rosa, Thomas W. Dyer, Oleg Gluschenkov, Jack A. Mandelman, Carl J. Radens, Alvin W. Strong
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Patent number: 6762966Abstract: An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.Type: GrantFiled: January 8, 2003Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Giuseppe LaRosa, Alvin W. Strong
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Publication number: 20040130957Abstract: An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor, allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.Type: ApplicationFiled: January 8, 2003Publication date: July 8, 2004Applicant: International Business Machines Corp;Inventors: Giuseppe LaRosa, Alvin W. Strong
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Patent number: 6750530Abstract: A programmable device including: an antifuse; a resistive heating element having a substantially temperature to power response, the resistive heating element adjacent to but not in contact with the antifuse; and means for passing an electric current through the resistive heating element in order to generate heat to raise the temperature of the antifuse sufficiently high enough to decrease a programming voltage of the antifuse, a time the programming voltage is applied to the antifuse or both the programming voltage of the antifuse and the time the programming voltage is applied to the antifuse.Type: GrantFiled: June 3, 2003Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: William A. Klaasen, Alvin W. Strong, Ernest Y. Wu