Abstract: The technology disclosed in this patent document can be used to construct devices with opto-electronic circuitry for sensing and identification applications, to provide untethered devices for deployment in living objects and other applications, and to provide fabrication techniques for making such devices for commercial production. As illustrated by specific examples disclosed herein, the disclosed technology can be implemented to provide fabrication methods, substrates, and devices that enable wireless, inorganic cell-scaled sensor and identification systems that are optically-powered and optically-readout.

Abstract: Systems and methods for producing a frequency divider output signal having a period substantially equal to three times a period of a reference input signal, comprising configuring each of three storage elements to receive a first input, a second input, and a reference input signal, and to provide a storage element output, obtaining a frequency divider output signal from at least one storage element output, and using the storage element output from each of the three storage elements as an input to another one of the three storage elements, where a phase difference between the output of the first storage element and the output of the second storage element is substantially equal to 60°.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A system is disclosed for interfacing a wireless communication device baseband module and a radio frequency integrated circuit. The system accepts a control signal from the baseband module. The control signal from the baseband module is generally at a first baseband voltage. The first baseband voltage is generally the baseband operating voltage level. The system distributes the control signal, via data latches, to a plurality of local level shifters. The plurality of local level shifters are associated with components of the radio frequency integrated circuit. The local level shifters convert the control signal to a shifted control signal at a second voltage level. The second voltage level is generally the component operating voltage. The shifted control signal may be maintained at the component while the radio frequency integrated circuit is intermittently shutdown. The system eliminates the need to reprogram radio frequency integrated circuit components after the shutdown period.

Abstract: A frequency divider has two or more storage elements connected in a loop. One of the outputs of each storage element is connected to one of the inputs of another storage element. Each storage element provides at least one output signal having a period equal to the period of a reference input signal multiplied by the number of interconnected storage elements. The reference input signal may be, for example, a local oscillator (“LO”) signal. In the case where the reference input signal has a 50% duty cycle, the output signals will also have a 50% duty cycle. Furthermore, in the case where a total of three storage elements are connected in a loop, the outputs of two of the three storage elements can be combined to provide a signal having substantially no third order harmonics.

Abstract: A receiver front end is provided with a low-noise amplifier (LNA), a linearity on demand (LOD) circuit, and a gain calibration device. The LOD circuit provides current to the LNA depending on linearity requirements. The gain calibration device monitors the amount of current provided by the LOD circuit to the LNA and provides signals to help compensate for variations in the LNA's gain due to the variations in the current supplied to the LNA by the LOD circuit. The compensation signals may be used to adjust the gain of a variable-gain amplifier, or may comprise compensation parameters usable by a digital signal processor, to compensate for the gain variations.

Abstract: A direct conversion receiver for receiving a first input signal and directly downconverting it to baseband frequencies. The receiver includes a frequency translator which is responsive to a phase-split input signal having 2n components, wherein n is an integer greater than 1. The phase-split signal has a period T which is about n times the period of the first input. The frequency translator alternates, at a rate of about 2n/T, between switching the first input signal to a first output, and switching the first signal to a second output. A preprocessor is available to improve the switching characteristics of the phase-split input signal.

Abstract: Systems for controlling the frequency of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system comprises a controllable oscillator and a frequency control circuit. The controllable oscillator is configured to generate an output signal that has a predefined frequency. The controllable oscillator is also configured with a plurality of operational states that are controlled by the frequency control circuit. Each operational state of the controllable oscillator defines a distinct frequency for the output signal of the controllable oscillator. The frequency control circuit receives the output signal of the controllable oscillator and determines the distinct frequency for the output signal that best approximates the predefined frequency.

Abstract: A polyphase filter for wireless communication systems includes at least two phase splitting filters each having a variable resistance across their respective outputs. The variable resistance can take any suitable form, such as a MOS transistor biased in the linear (triode) region, a bipolar differential pair, or a digitally switchable resistance. The phase adjustment required for a particular filter can be identified and adjusted through either a closed loop system or an open loop system. Adjustment of the variable resistance reduces quadrature error.

Abstract: Various apparatus and method embodiments are disclosed.

Abstract: Embodiments of the invention provide techniques for calibrating voltage-controlled oscillators (VCOs). Multiple VCOs may be disposed on a chip with the VCOs having different frequency ranges. The VCOs may be selected and tested to determine a desired VCO to use to tune to a selected channel frequency. Each of the VCOs has multiple possible varactor configurations. The varactor configurations of the desired VCO determined to be used to tune to the selected channel frequency can be selected and tested to determine a desired varactor configuration for the desired VCO. The desired VCO with the desired varactor configuration will preferably be able to produce a full range of desired frequencies corresponding to all channel frequencies desired.

Abstract: A subharmonic mixer and a method of downconverting a received radio frequency signal is described. The subharmonic mixer of the present invention uses two stacks of switching cores with high order symmetry to reduce unwanted harmonic generation and uses transistors to improve headroom.

Abstract: Double balanced mixers having transistor pairs are affected by area mismatches between the transistors. The area mismatches can be represented as a ratio between the mixer core transistors that is directly related to voltage. Thus, an input voltage into one of the mixer core transistors in a transistor pair can compensate for the area mismatch. The compensation is achieved by a voltage track and hold feedback loop to one of the mixer core transistors.

Abstract: A programmable frequency divider capable of a 50% duty cycle at odd and even integer division ratios.

Abstract: A mixing system divides a local oscillator (“LO”) signal into two signals having a predetermined phase difference, mixes each of the two signal with an input signal to produce a mixed signal, and then combines the mixed signals to produce an output signal having substantially no third-order mixing products.

Abstract: An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.

Abstract: Systems for controlling the amplitude of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system provides a circuit having a controllable oscillator and an amplitude control circuit. The controllable oscillator is configured to generate an output signal having a predefined frequency and a predefined amplitude. The controllable oscillator is also configured with a plurality of operational states that are controlled by the amplitude control circuit. Each operational state of the controllable oscillator defines a particular current bias associated with a distinct amplitude of the output signal of the controllable oscillator. The amplitude control circuit receives the output signal of the controllable oscillator and determines the amplitude. When the amplitude of the output signal of the controllable oscillator is less than the predefined amplitude, the amplitude control circuit provides a control signal to the controllable oscillator.

Abstract: Systems for reducing the parasitic effects of a transistor-based switch are provided. In one such system provides a transistor circuit for implementing a switch having reduced parasitic effects. In general, the transistor circuit comprises a first switch node, a second switch node, a third switch node, a transistor device, and a circuit configured to reduce the parasitic characteristics of the transistor device. The first switch node is for connecting to one node of an external circuit. The second switch node is for connecting to a second node of an external circuit. The transistor device is a three-terminal device. The first terminal is connected to the first switch node. The second terminal is connected to the second switch node. The third terminal is for receiving a control signal that operates the transistor circuit as a switch by controlling the electrical connectivity between the first terminal and the second terminal. The third switch node is for receiving the control signal.

Abstract: A subharmonic mixer and a method of downconverting a received radio frequency signal is described. The subharmonic mixer of the present invention uses two stacks of switching cores with high order symmetry to reduce unwanted harmonic generation and uses transistors to improve headroom.