Abstract: A tuning circuit for use in tuning multiple voltage-controlled oscillators (VCOs) of a phase-locked loop (PLL) is provided. A search algorithm is used to determine which VCO to use for a given frequency to be synthesized by the PLL. The tuning circuit provides a binary representation, associated with the frequency to synthesize, to the PLL. The PLL responds to this representation by attempting to synthesize the associated frequency. New binary representations are provided until an indication of a threshold frequency between multiple VCOs is determined. A record of the threshold frequency is stored. The binary representation of a frequency to be synthesized and the stored record of the threshold frequency are used to provide an indication of which VCO of the PLL to use to synthesize the desired frequency.

Abstract: A programmable frequency divider capable of a 50% duty cycle at odd and even integer division ratios. In one embodiment, the frequency divider is configured to produce an output signal having a period equal to a division ratio N times a period of a clock signal, and the division number N is a programmable variable which bears the following relationship to the number F of required storage elements: F = N + P 2 , where P is 1 if the division ratio is odd, and 0 if the division ratio is even.

Abstract: A system is disclosed for transmitting and receiving signals. The system includes the use of a frequency plan table a system for creating the frequency plan table. The frequency plan table relates carrier frequency channels to the operation of a synthesizer and a plurality of programmable frequency dividers in a locked loop. In a transmitter, a first programmable frequency divider accepts a reference signal and produces a comparison signal. A mixer accepts the reference signal and a transmission signal and produces a loop signal. A second programmable frequency divider accepts the loop signal and produces a loop signal having a divided intermediate frequency signal. A phase detector compares the comparison signal and the loop signal having a divided intermediate frequency and produces an output that controls a variable controlled oscillator. The variable controlled oscillator produces a modulated transmission signal.

Abstract: An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.

Abstract: A direct conversion receiver for receiving a first input signal and directly downconverting it to baseband frequencies. The receiver includes a frequency translator which is responsive to a phase-split input signal having 2n components, wherein n is an integer greater than 1. The phase-split signal has a period T which is about n times the period of the first input. The frequency translator alternates, at a rate of about 2n/T, between switching the first input signal to a first output, and switching the first signal to a second output. A preprocessor is available to improve the switching characteristics of the phase-split input signal.

Abstract: A direct conversion receiver for receiving a first input signal and directly downconverting it to baseband frequencies. The receiver includes a frequency translator which is responsive to a phase-split input signal having 2n components, wherein n is an integer greater than 1. The phase-split signal has a period T which is about n times the period of the first input. The frequency translator alternates, at a rate of about 2n/T, between switching the first input signal to a first output, and switching the first signal to a second output. A preprocessor is available to improve the switching characteristics of the phase-split input signal.

Abstract: The DC offset compensator compensates DC offsets resulting from interferor self mixing and interferor interaction with even-order nonlinearities. In one embodiment, the DC offset compensator resides in a mobile communication device. A radio frequency (RF) communication signal is mixed with a local oscillator signal (LO) in a direct conversion mixer. The communication signal, at certain times, will have both a communication signal of interest and interferor signals. The interferor signals induce signals in other portions of the mixer circuit, called interferor leakage signals, and the interaction between the two signals causes undesirable DC offsets in the mixer output. The DC offset compensator detects the presence of the interferor signals and provides a compensating signal to the output of the mixer such that the undesirable DC offset signals caused by the interferer self mixing and interferor interaction with even order-nonlinearities in the mixer are compensated out of the mixer output signal.

Abstract: Systems for controlling the amplitude of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system provides a circuit having a controllable oscillator and an amplitude control circuit. The controllable oscillator is configured to generate an output signal having a predefined frequency and a predefined amplitude. The controllable oscillator is also configured with a plurality of operational states that are controlled by the amplitude control circuit. Each operational state of the controllable oscillator defines a particular current bias associated with a distinct amplitude of the output signal of the controllable oscillator. The amplitude control circuit receives the output signal of the controllable oscillator and determines the amplitude. When the amplitude of the output signal of the controllable oscillator is less than the predefined amplitude, the amplitude control circuit provides a control signal to the controllable oscillator.

Abstract: Double balanced mixers having transistor pairs are affected by area mismatches between the transistors. The area mismatches can be represented as a ratio between the mixer core transistors that is directly related to voltage. Thus, an input voltage into one of the mixer core transistors in a transistor pair can compensate for the area mismatch. The compensation is achieved by a voltage track and hold feedback loop to one of the mixer core transistors.

Abstract: A system is disclosed for transmitting and receiving signals. The system includes the use of a frequency plan table a system for creating the frequency plan table. The frequency plan table relates carrier frequency channels to the operation of a synthesizer and a plurality of programmable frequency dividers in a locked loop. In a transmitter, a first programmable frequency divider accepts a reference signal and produces a comparison signal. A mixer accepts the reference signal and a transmission signal and produces a loop signal. A second programmable frequency divider accepts the loop signal and produces a loop signal having a divided intermediate frequency signal. A phase detector compares the comparison signal and the loop signal having a divided intermediate frequency and produces an output that controls a variable controlled oscillator. The variable controlled oscillator produces a modulated transmission signal.

Abstract: A GmC filter that suppresses unwanted signals generated by a GmC compression stage. The GmC filter utilizes the same compression stage for the decompression stages. By using the same compression stage for the decompression stages unwanted in-band signals generated by the compression stage are suppressed. Further, over all circuitry is decreased, power is saved, and GmC filter design is simplified.

Abstract: Systems for controlling the amplitude of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system provides a circuit having a controllable oscillator and an amplitude control circuit. The controllable oscillator is configured to generate an output signal having a predefined frequency and a predefined amplitude. The controllable oscillator is also configured with a plurality of operational states that are controlled by the amplitude control circuit. Each operational state of the controllable oscillator defines a particular current bias associated with a distinct amplitude of the output signal of the controllable oscillator. The amplitude control circuit receives the output signal of the controllable oscillator and determines the amplitude. When the amplitude of the output signal of the controllable oscillator is less than the predefined amplitude, the amplitude control circuit provides a control signal to the controllable oscillator.

Abstract: Systems for controlling the frequency of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system comprises a controllable oscillator and a frequency control circuit. The controllable oscillator is configured to generate an output signal that has a predefined frequency. The controllable oscillator is also configured with a plurality of operational states that are controlled by the frequency control circuit. Each operational state of the controllable oscillator defines a distinct frequency for the output signal of the controllable oscillator. The frequency control circuit receives the output signal of the controllable oscillator and determines the distinct frequency for the output signal that best approximates the predefined frequency.

Abstract: The DC offset compensator compensates DC offsets resulting from interferor self mixing and interferor interaction with even-order nonlinearities. In one embodiment, the DC offset compensator resides in a mobile communication device. A radio frequency (RF) communication signal is mixed with a local oscillator signal (LO) in a direct conversion mixer. The communication signal, at certain times, will have both a communication signal of interest and interferor signals. The interferor signals induce signals in other portions of the mixer circuit, called interferor leakage signals, and the interaction between the two signals causes undesirable DC offsets in the mixer output. The DC offset compensator detects the presence of the interferor signals and provides a compensating signal to the output of the mixer such that the undesirable DC offset signals caused by the interferer self mixing and interferor interaction with even order-nonlinearities in the mixer are compensated out of the mixer output signal.

Abstract: A system is disclosed for interfacing a wireless communication device baseband module and a radio frequency integrated circuit. The system accepts a control signal from the baseband module. The control signal from the baseband module is generally at a first baseband voltage. The first baseband voltage is generally the baseband operating voltage level. The system distributes the control signal, via data latches, to a plurality of local level shifters. The plurality of local level shifters are associated with components of the radio frequency integrated circuit. The local level shifters convert the control signal to a shifted control signal at a second voltage level. The second voltage level is generally the component operating voltage. The shifted control signal may be maintained at the component while the radio frequency integrated circuit is intermittently shutdown. The system eliminates the need to reprogram radio frequency integrated circuit components after the shutdown period.

Abstract: A direct conversion receiver comprising a preprocessor coupled to a frequency translator which, in one implementation, is a modified Gilbert mixer. In one embodiment, the preprocessor imparts desired characteristics to split-phase signals received from a local oscillator, including transition points which are determined by crossings through a DC offset, substantial symmetry about a DC offset, and steep transitions about the transition points. In one embodiment, the period of the signals from the local oscillator is divided into portions, and only one of the output signals from the preprocessor is asserted in a predefined state at a time, the predefined state determined effective to reverse polarity of the mixer, signals and a related frequency translator which is responsive to the signals. The frequency translator has a first input at a first input frequency, and at least one second input at a second frequency.

Abstract: A system for an eight-phase 45° polyphase filter with amplitude matching, where a full eight-phase 45° split may be achieved by tying together the inputs of two offset four-phase 90° phase splitters. Amplitude matching may be achieved by obtaining those inputs from an additional single four-phase 90° phase splitter. The additional phase splitter can distribute power evenly among the inputs of the two offset phase splitters so as to cancel out the occurrence of any uneven power distribution.

Abstract: A subharmonic mixer that has two switching stages is used to improved mixer gain in a direct downconversion receiver. The first switching stage mixes a received RF signal to an intermediate frequency that is one-half the received RF signal frequency. The second switching stage mixes the intermediate frequency to baseband. By connecting the two switching stages in series, current is reused and harmonic content from the first stage is fed into the second stage thereby improving the mixer gain.

Abstract: A filter system having a variable dynamic range window comprising a parameter detector, a biasing unit and an active filter network. In one implementation, the active filter network comprises a log-domain filter. The parameter detector is configured to detect a parameter of a signal. The biasing unit, responsive thereto, biases the incoming signal. In one implementation, the biasing unit biases the signal to avoid zero crossings thereof. The effect is to adjust the dynamic range window of the filter to achieve an effective dynamic range which is greater than the nominal dynamic range.